Commit d163c40a authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

better setting of nand ecc step size

parent df2ceddc
......@@ -313,7 +313,6 @@
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
nand-ecc-mode = "on-die";
nand-ecc-step-size = <2048>;
/*arm,nand-clk-freq-hz = <0x5f5e100>;*/
arm,nand-width = <0x8>;
arm,nand-cycle-t0 = <0x4>;
......
......@@ -744,10 +744,7 @@ static int micron_nand_init(struct nand_chip *chip)
&micron_nand_on_die_8_ooblayout_ops);
chip->ecc.bytes = chip->ecc_strength_ds * 2;
// this is already read from the device tree
if (!chip->ecc.size){
chip->ecc.size = 512;
}
chip->ecc.size = 512;
chip->ecc.strength = chip->ecc_strength_ds;
chip->ecc.algo = NAND_ECC_BCH;
chip->ecc.read_page = micron_nand_read_page_on_die_ecc;
......
......@@ -1341,7 +1341,11 @@ static int pl353_nand_probe(struct platform_device *pdev)
xnfc->buswidth = val;
chip->chip_delay = 30;
/* Set the device option and flash width */
chip->options = NAND_BUSWIDTH_AUTO;
// old:
//chip->options = NAND_BUSWIDTH_AUTO;
// new: MT29F8G08ADBDAH4 does not support subpage write,
// setting here, will change later
chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE;
chip->bbt_options = NAND_BBT_USE_FLASH;
platform_set_drvdata(pdev, xnfc);
chip->setup_data_interface = pl353_setup_data_interface;
......
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