Commit b34fa5a2 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

true freq is 22MHz for MT9F002

parent ed39bd0a
This diff is collapsed.
......@@ -20,26 +20,45 @@
#define MT9F002_PARTID 0x2E01 ///< MT9F002 PartID register value
#define MT9F002_I2C_ADDR 0x10 ///< MT9P I2C slave address (7 bit)
// bit 9 should have set masking for broken frames
#define MT9F002_RESET_REGISTER_VALUE 0x001c
// number of lines to sacrifice before generating Frame Valid
#define MT9F002_VACT_DELAY 2
// Clocks, this is basis
// from x393_parameters.vh:
// 220MHz -> 22MHz - the real clock is 22MHz - that's why multiplier is 0xb4
// The 3 parameters below are needed to calculate sensor clock
// line 568
#define PXD_CLK_DIV 10
// line 940
#define CLKFBOUT_MULT_PCLK 36, // 880 MHz
// line 941
#define CLKOUT_DIV_PCLK 4, // 220 MHz
// note: there is also DIVCLK_DIVIDE_PCLK
#define MT9F002_IFACE_CLK 24444000*PXD_CLK_DIV/CLKFBOUT_MULT_PCLK/CLKOUT_DIV_PCLK
// External sensor clock before pll
// Constant = 24.444MHz in Hz
#define MT9F002_EXT_CLK 24444000
// This is not a constant = 24.444MHz in Hz
#define MT9F002_EXT_CLK MT9F002_IFACE_CLK
// Virtual pixel clock is used as the basis for frame timing equations.
// Constant = 244.44MHz in Hz
#define MT9F002_VT_PIX_CLK 244440000
// Constant = 220MHz in Hz
#define MT9F002_VT_PIX_CLK 220000000
// OP_PIX_CLK
#define MT9F002_OP_PIX_CLK 110000000
// Serial output clock
// Constant = 733.32MHz in Hz
#define MT9F002_OP_SYS_CLK 733320000
// Constant = 660MHz in Hz
#define MT9F002_OP_SYS_CLK 660000000
// Sensor clock dividers and multiplier
// These should be calculated based on the clocks above
// pll multiplier
// pll multiplier, default is 0xa5 (165), also tried 0xa2 (162)
#define MT9F002_PLL_MULTIPLIER_VALUE 0xb4
// pre_pll_clk_div (0x0304), default value is 0x6
#define MT9F002_PRE_PLL_CLK_DIV_VALUE 0x6
......@@ -603,7 +622,14 @@
#define P_MT9F002_X_OUTPUT_SIZE 26
#define P_MT9F002_LINE_LENGTH_PCK 27
#define P_MT9F002_READ_MODE 28
#define P_MT9F002_X_ODD_INC 28
#define P_MT9F002_MIN_LINE_BLANKING_PCK 29
#define P_MT9F002_MIN_LINE_LENGTH_PCK 30
#define P_MT9F002_FRAME_LENGTH_LINES 31
#define P_MT9F002_MIN_FRAME_BLANKING_LINES 32
#define P_MT9F002_READ_MODE 33
//#define P_REG(x) x
......
......@@ -360,7 +360,7 @@
/**
* \def D(x) optional debug output
* \def D(x) optional debug output
*/
#if ELPHEL_DEBUG
......@@ -629,31 +629,31 @@ static unsigned short sensor_reg_copy[SENSOR_PORTS][256]; ///< Read all 256 sens
// a place to add some general purpose register writes to sensors during init
/** Register initial writes for MT9M001 */
static unsigned short mt9m001_inits[]=
static unsigned short mt9m001_inits[]=
{
};
/** Register initial writes for MT9D001 */
static unsigned short mt9d001_inits[]=
static unsigned short mt9d001_inits[]=
{
P_MT9X001_CALTHRESH , 0xa39d,
P_MT9X001_CALCTRL, 0x8498
};
/** Register initial writes for MT9T031 */
static unsigned short mt9t001_inits[]=
static unsigned short mt9t001_inits[]=
{
};
/** Register initial writes for MT9P006 */
static unsigned short mt9p001_inits[]=
static unsigned short mt9p001_inits[]=
{
// P_MT9X001_OUTCTRL, 0x2, // set slowest output signals (clock and non-clock) to reduce EMI (for FCC part 15)
P_MT9X001_OUTCTRL, 0x1f82, // NC393: Restoring default, will adjust later
P_MT9X001_7F , 0x0 // Should be written 0 to prevent blue "blooming" columns
};
/** Specifying sensor registers to be controlled individually in multi-sensor applications, MT9M001 */
static unsigned short mt9m001_multiregs[]=
static unsigned short mt9m001_multiregs[]=
{
P_MT9X001_ROWSTART,
P_MT9X001_COLSTART,
......@@ -673,7 +673,7 @@ static unsigned short mt9m001_multiregs[]=
};
/** Specifying sensor registers to be controlled individually in multi-sensor applications, MT9D001 */
static unsigned short mt9d001_multiregs[]=
static unsigned short mt9d001_multiregs[]=
{
P_MT9X001_ROWSTART,
P_MT9X001_COLSTART,
......@@ -693,7 +693,7 @@ static unsigned short mt9d001_multiregs[]=
};
/** Specifying sensor registers to be controlled individually in multi-sensor applications, MTTM031 */
static unsigned short mt9t001_multiregs[]=
static unsigned short mt9t001_multiregs[]=
{
P_MT9X001_ROWSTART,
P_MT9X001_COLSTART,
......@@ -713,7 +713,7 @@ static unsigned short mt9t001_multiregs[]=
};
/** Specifying sensor registers to be controlled individually in multi-sensor applications, MT9P006 */
static unsigned short mt9p001_multiregs[]=
static unsigned short mt9p001_multiregs[]=
{
P_MT9X001_ROWSTART,
P_MT9X001_COLSTART,
......@@ -758,7 +758,7 @@ int mt9x001_pgm_sensorregs (int sensor_port, struct sensor_t * sensor, struct
* -- initialize appropriate P_* registers (including sensor register shadows) - that initialization will schedule related pgm_* functions
*
* TODO: when is P_CLK_FPGA initialized? Needs to be done before this
* hardware i2c is expected to be reset and initialized - no wrong, it will be programmed in
* hardware i2c is expected to be reset and initialized - no wrong, it will be programmed in
* onchange_i2c should be the first after init sensor (even before onchange_sensorphase)
* onchange_sensorphase will be triggered after this
* hardware i2c after this function will be disabled, will need onchange_sensorphase to initialize/start it.
......@@ -1043,7 +1043,7 @@ int mt9x001_pgm_initsensor (int sensor_port, ///< sensor port
MDF4(for (i=0; i<1023; i++) {if ((i & 0x1f)==0) dev_dbg(g_dev_ptr,"\n"); dev_dbg(g_dev_ptr," 0x%06lx",GLOBALPARS (sensor_port, G_SENSOR_CALIB+i));});
return 0;
}
}
/** Program sensor WOI and mirroring
......@@ -1397,7 +1397,7 @@ int mt9x001_pgm_limitfps (int sensor_port, ///< sensor port numb
//pgm_limitfps
/* NOTE: Was this for a long time - make sure replacement does not break anything !!!
*
int wh = thispars->pars[P_SENSOR_REGS+P_MT9X001_HEIGHT] + 1;
int wh = thispars->pars[P_SENSOR_REGS+P_MT9X001_HEIGHT] + 1;
int dv = thispars->pars[P_DCM_VERT];
int height = 2 * (wh / (2 * dv));
if((height * dv) < wh) height++;
......@@ -1809,7 +1809,7 @@ int mt9x001_pgm_gains (int sensor_port, ///< sensor port numb
limitsModified+=2;
if (maxAnaGain > (sensor->maxGain256 << 8)) { ///sensor->maxGain256 is not calibrated, so digital gain should be able to accomodate for variations
maxAnaGain = (sensor->maxGain256 << 8);
SETFRAMEPARS_SET(P_GAIN_MIN, maxAnaGain);
SETFRAMEPARS_SET(P_GAIN_MAX, maxAnaGain);
}
}
// maxGain= maxAnaGain * (MAX_DIGITAL_GAIN >> 8);
......@@ -2167,7 +2167,7 @@ int mt9x001_pgm_sensorregs (int sensor_port, ///< sensor port
}
if (nupdate) setFramePars(sensor_port,thispars, nupdate, pars_to_update); // save changes to sensor register shadows
return 0;
}
}
//static short sensor_reg_copy[SENSOR_PORTS][256]; // Read all 256 sensor registers here - during initialization and on demand
// // Later may increase to include multiple subchannels on 10359
......
......@@ -506,7 +506,8 @@ int pgm_detectsensor (int sensor_port, ///< sensor port number (
// ************************************************************************************************
}
setFramePar(sensor_port, thispars, P_CLK_FPGA, 200000000); // FIXME: NC393
//setFramePar(sensor_port, thispars, P_CLK_FPGA, 200000000); // FIXME: NC393
setFramePar(sensor_port, thispars, P_CLK_FPGA, 240000000);
// Freqs for sensors
if ((thispars->pars[P_SENSOR]==0) &&
......
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