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linux-elphel
Commit 7e2ae73e authored by Andrey Filippov's avatar Andrey Filippov
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implemented multiple ports setting using driver write method

parent e7e0c7be
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Showing with 170 additions and 82 deletions
src/drivers/elphel/framepars.c
View file @ 7e2ae73e
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src/drivers/elphel/framepars.h
View file @ 7e2ae73e
......@@ -17,6 +17,7 @@ int initSequencers (int sensor_port); ///Move to sensorcommon? currently it
void initGlobalPars (int sensor_port); /// resets all global parameters but debug mask (if ELPHEL_DEBUG)
int initMultiPars (int sensor_port); /// initialize structures for individual per-sensor parameters. Now only works for sensor registers using G_MULTI_REGSM. Should be called aftre/during sensor detection
void initFramePars (int sensor_port); ///initialize all parameters, set thisFrameNumber to frame16 (read from hardware, usually 0 after resetting i2c and cmd_seq)
void stopFrameSequencer(int sensor_port, int dis_int);
void resetFrameNumber (int sensor_port, u32 aframe, int hreset); /// reset this frame number (called from initFramePars(), also can be used to avoid frame number integer overflow)
unsigned long get_imageParamsFrame(int sensor_port, int n, int frame);
......
src/drivers/elphel/multi10359.c
View file @ 7e2ae73e
......@@ -1002,7 +1002,7 @@ int multisensor_pgm_detectsensor (int sensor_port, ///< sensor p
int i;
int this_sensor_type;
long * multiOutDelay;
x393_sens_mode_t sens_mode = {.d32=0}; // to disable senosr channel and prevent SoF pulses while 10359 memory is being trained
x393_sens_mode_t sens_mode = {.d32=0}; // to disable senor channel and prevent SoF pulses while 10359 memory is being trained
sens_mode.chn_en = 0;
sens_mode.chn_en_set = 1;
X393_SEQ_SEND1 (sensor_port, frame16, x393_sens_mode, sens_mode);
......
src/drivers/elphel/pgm_functions.c
View file @ 7e2ae73e
......@@ -1260,6 +1260,10 @@ int pgm_limitfps (int sensor_port, ///< sensor port number (0..3
// if (async && (thispars->pars[P_TRIG_PERIOD] >=256)) { // <256 - single trig
// if (async && (thispars->pars[P_TRIG_PERIOD] !=1)) { // <256 - single trig, here only ==1 is for single
// Update period to comply even if it is not in async mode
if (!thispars->pars[P_CLK_SENSOR]){ // not initialized
dev_dbg(g_dev_ptr,"{%d} P_CLK_SENSOR == 0, abort command\n",sensor_port);
return -1;
}
if (thispars->pars[P_TRIG_PERIOD] !=1) { // <256 - single trig, here only ==1 is for single
min_period_camsync = sensor_to_camsync(min_period, thispars->pars[P_CLK_SENSOR]);
if (thispars->pars[P_TRIG_PERIOD] < min_period_camsync) SETFRAMEPARS_SET(P_TRIG_PERIOD, min_period_camsync); // set it (and propagate to the later frames)
......@@ -1306,7 +1310,6 @@ int pgm_triggermode(int sensor_port, ///< sensor port number (0..3
dev_dbg(g_dev_ptr,"{%d} frame16=%d\n",sensor_port,frame16);
MDP(DBGB_PSFN, sensor_port,"frame16=%d\n",frame16)
if (frame16 >= PARS_FRAMES) return -1; // wrong frame
#ifndef NC353
camsync_mode.trig = (thispars->pars[P_TRIG] & 4)?1:0;
if (camsync_mode.trig) { // if trigger mode, enable camsync module, if off - do nothing
camsync_mode.en = 1;
......@@ -1320,13 +1323,17 @@ int pgm_triggermode(int sensor_port, ///< sensor port number (0..3
// set directly, bypassing sequencer as it may fail with wrong trigger
x393_camsync_mode (camsync_mode);
MDP(DBGB_PADD, sensor_port,"x393_camsync_mode(0x%x)\n",camsync_mode.d32)
// now update common trigger parameters and mark dependent channels to update, if anything changed;
if (thispars->pars[P_TRIG] != common_pars->trig_mode){
int i;
dev_dbg(g_dev_ptr,"{%d} Updating common trigger mode, old=0x%lx, new=0x%lx\n",sensor_port,common_pars->trig_mode,thispars->pars[P_TRIG]);
common_pars->trig_mode = thispars->pars[P_TRIG];
for (i=0; i<SENSOR_PORTS; i++) if (i != sensor_port) {
common_pars->updated[i] = 1;
}
}
return 0;
#else
// int fpga_addr= frame16;
// int async=(thispars->pars[P_TRIG] & 4)?1:0;
X3X3_SEQ_SEND1(frame16, X313_WA_DCR0, X353_DCR0(SENSTRIGEN,async));
return 0;
#endif
}
......@@ -2432,7 +2439,6 @@ int pgm_trigseq (int sensor_port, ///< sensor port number (0..3
int d;
int is_master = 0;
int update_master_channel = 0; // set if any of the common (not channel-specific) parameters is modified
#ifndef NC353
x393_camsync_io_t camsync_src = {.d32=0};
x393_camsync_io_t camsync_dst = {.d32=0};
x393_gpio_set_pins_t gpio_set_pins = {.d32=0};
......@@ -2561,66 +2567,6 @@ int pgm_trigseq (int sensor_port, ///< sensor port number (0..3
common_pars->updated[0],common_pars->updated[1],common_pars->updated[2],common_pars->updated[3]);
}
return 0;
#else
dev_dbg(g_dev_ptr,"{%d} frame16=%d\n",sensor_port,frame16);
if (frame16 >= PARS_FRAMES) return -1; // wrong frame
if (frame16 >= 0) return -1; // ASAP only mode
// Trigger condition changed? (0 - internal sequencer)
if (FRAMEPAR_MODIFIED(P_TRIG_CONDITION)) {
port_csp0_addr[X313_WA_CAMSYNCTRIG] = thispars->pars[P_TRIG_CONDITION];
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_CAMSYNCTRIG, (int)thispars->pars[P_TRIG_CONDITION]);
}
// Trigger delay changed?
if (FRAMEPAR_MODIFIED(P_TRIG_DELAY)) {
port_csp0_addr[X313_WA_CAMSYNCDLY] = thispars->pars[P_TRIG_DELAY];
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_CAMSYNCDLY, (int) thispars->pars[P_TRIG_DELAY]);
}
// Sequencer output word changed? (to which outputs it is sent and what polarity)
if (FRAMEPAR_MODIFIED(P_TRIG_OUT)) {
port_csp0_addr[X313_WA_CAMSYNCOUT] = thispars->pars[P_TRIG_OUT];
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_CAMSYNCOUT, (int) thispars->pars[P_TRIG_OUT]);
// Enable connection from the trigger module to the FPGA GPIO pins
if (thispars->pars[P_TRIG_OUT]!=0) {
port_csp0_addr[X313_WA_IOPINS] = X313_WA_IOPINS_EN_TRIG_OUT;
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_IOPINS, (int) X313_WA_IOPINS_EN_TRIG_OUT);
} else {
// Not needed, I think
// port_csp0_addr[X313_WA_IOPINS] = X313_WA_IOPINS_DIS_TRIG_OUT;
// dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_IOPINS, (int) X313_WA_IOPINS_DIS_TRIG_OUT);
}
}
// Sequencer period changed? (0 - stopped, 1 - single trigger, >=256 - start repetitive)
if (FRAMEPAR_MODIFIED(P_TRIG_PERIOD)) {
if (unlikely((thispars->pars[P_TRIG_PERIOD] > 1) && (thispars->pars[P_TRIG_PERIOD] < 256))) { // Wrong value, restore old one
SETFRAMEPARS_SET(P_TRIG_PERIOD,prevpars->pars[P_TRIG_PERIOD]);
} else {
port_csp0_addr[X313_WA_CAMSYNCPER] = thispars->pars[P_TRIG_PERIOD];
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_CAMSYNCPER, (int)thispars->pars[P_TRIG_PERIOD]);
}
}
// Bit length changed or not yet initialized?
if (FRAMEPAR_MODIFIED(P_TRIG_BITLENGTH) || (thispars->pars[P_TRIG_BITLENGTH]==0)) {
d=thispars->pars[P_TRIG_BITLENGTH];
if (unlikely((d<2) || (d>255))) { // Wrong value, restore old one
d=P_TRIG_BITLENGTH_DEFAULT;
SETFRAMEPARS_SET(P_TRIG_BITLENGTH,d);
}
port_csp0_addr[X313_WA_CAMSYNCPER] = d;
dev_dbg(g_dev_ptr,"{%d} writing bit length-1: port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_CAMSYNCPER, d);
}
// P_EXTERN_TIMESTAMP changed? (0 - internal sequencer)
if (FRAMEPAR_MODIFIED(P_EXTERN_TIMESTAMP)) {
port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EXTERNALTS,thispars->pars[P_EXTERN_TIMESTAMP]?1:0);
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_DCR1, (int)X353_DCR1(EXTERNALTS,thispars->pars[P_EXTERN_TIMESTAMP]?1:0));
}
// P_XMIT_TIMESTAMP changed? (0 - internal sequencer)
if (FRAMEPAR_MODIFIED(P_XMIT_TIMESTAMP)) {
port_csp0_addr[X313_WA_DCR1]=X353_DCR1(OUTPUTTS,thispars->pars[P_XMIT_TIMESTAMP]?1:0);
dev_dbg(g_dev_ptr,"{%d} port_csp0_addr[0x%x]=0x%x\n",sensor_port, (int) X313_WA_DCR1, (int)X353_DCR1(OUTPUTTS,thispars->pars[P_XMIT_TIMESTAMP]?1:0));
}
if (nupdate) setFramePars(sensor_port, thispars, nupdate, pars_to_update); // save changes, schedule functions
return 0;
#endif
}
/** Program smart IRQ mode (needs to be on, at least bit 0)
......
src/include/uapi/elphel/c313a.h
View file @ 7e2ae73e
......@@ -1012,8 +1012,13 @@ struct common_pars_t{
unsigned long xmit_timestamp; ///< Transmit timestamp with sync pulse
unsigned long trig_condition; ///< Trigger condition (Each dibit: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high)
unsigned long trig_out; ///< trigger output (Each dibit: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high)
unsigned long trig_mode; ///< trigger_mode (0: free running, 4 - ERS snapshot, 20 - GRR
};
/*
#define TRIGMODE_FREERUN 0
#define TRIGMODE_SNAPSHOT 4
#define TRIGMODE_GRR 20
* TRIG_PERIOD 500 0x1f4
* TRIG_BITLENGTH 31 0x1f
* EXTERN_TIMESTAMP 1 0x1
......@@ -1982,8 +1987,19 @@ struct huffman_encoded_t {
};
/// All other integer constants exported to PHP space (C:"CONSTANT" -> PHP:"ELPHEL_CONST_CONSTANT)
#define FRAME_ASAP -1 // use in PHP to specify ASAP through normal sequencer (current frame plus minimal latency)
#define FRAME_IMMED -2 // use in PHP to specify ASAP bypassing sequencer - works w/o frame sync pulses
#define TRIGMODE_FREERUN 0
#define TRIGMODE_SNAPSHOT 4
#define TRIGMODE_GRR 20
#define CONST_NAME_ENTRY(y) { y, #y }
#define DEFINE_CONST_NAMES(x) struct p_names_t x[]= { \
CONST_NAME_ENTRY(FRAME_IMMED), \
CONST_NAME_ENTRY(FRAME_ASAP), \
CONST_NAME_ENTRY(TRIGMODE_FREERUN), \
CONST_NAME_ENTRY(TRIGMODE_SNAPSHOT), \
CONST_NAME_ENTRY(TRIGMODE_GRR), \
CONST_NAME_ENTRY(SENSOR_RUN_STOP), \
CONST_NAME_ENTRY(SENSOR_RUN_SINGLE), \
CONST_NAME_ENTRY(SENSOR_RUN_CONT), \
......
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