synced with master - device tree and patches

src/arch/arm/boot/dts/elphel393-bootargs-mmc.dtsi

+/**/
+/ {
+	chosen {
+		bootargs = "cma=336M console=ttyPS0,115200 root=/dev/mmcblk0p2 rw ip=192.168.0.8 earlyprintk rootwait rootfstype=ext4";
+		linux,stdout-path = "/amba@0/serial@e0000000";
+	};
+};

src/arch/arm/boot/dts/elphel393-bootargs-nand.dtsi

+/**/
+/ {
+	chosen {
+		bootargs = "cma=336M console=ttyPS0,115200 root=ubi0:elphel393-rootfs rw ip=192.168.0.8 earlyprintk rootwait rootfstype=ubifs ubi.mtd=4,2048";
+		linux,stdout-path = "/amba@0/serial@e0000000";
+	};
+};

src/arch/arm/boot/dts/elphel393-bootargs-ram.dtsi

+/**/
+/ {
+	chosen {
+		bootargs = "cma=336M console=ttyPS0,115200 root=/dev/ram rw ip=192.168.0.8 earlyprintk ramdisk_size=262144";
+		linux,stdout-path = "/amba@0/serial@e0000000";
+	};
+};

src/patches/README

+Patches from this directory are applied by 'meta-elphel393/recipes-kernel/linux/linux-xlnx' bitbake recipe. To add a new patch, append SRC_URI variable in the recipe.

src/patches/ahci.patch

+--- a/drivers/ata/ahci.h	2016-09-13 17:18:35.579259846 -0600
++++ b/drivers/ata/ahci.h	2016-08-01 11:57:06.306630339 -0600
+@@ -396,6 +396,7 @@ void ahci_print_info(struct ata_host *ho
+ int ahci_host_activate(struct ata_host *host, int irq,
+ 		       struct scsi_host_template *sht);
+ void ahci_error_handler(struct ata_port *ap);
++irqreturn_t ahci_single_irq_intr(int irq, void *dev_instance);
+ 
+ static inline void __iomem *__ahci_port_base(struct ata_host *host,
+ 					     unsigned int port_no)

src/patches/drivers-elphel.patch

+diff -Naur a/drivers/Kconfig b/drivers/Kconfig
+--- a/drivers/Kconfig	2016-01-25 18:31:43.309779723 -0700
++++ b/drivers/Kconfig	2016-01-25 18:48:17.521798388 -0700
+@@ -182,4 +182,6 @@
+ 
+ source "drivers/android/Kconfig"
+ 
++source "drivers/elphel/Kconfig"
++
+ endmenu
+diff -Naur a/drivers/Makefile b/drivers/Makefile
+--- a/drivers/Makefile	2016-01-25 18:31:43.309779723 -0700
++++ b/drivers/Makefile	2016-01-25 18:50:39.545801055 -0700
+@@ -165,3 +165,6 @@
+ obj-$(CONFIG_THUNDERBOLT)	+= thunderbolt/
+ obj-$(CONFIG_CORESIGHT)		+= coresight/
+ obj-$(CONFIG_ANDROID)		+= android/
++
++obj-$(CONFIG_ELPHEL393)		+= elphel/
++obj-$(CONFIG_ELPHELDRVONMICROZED)	+= elphel/

src/patches/libahci.patch

+--- a/drivers/ata/libahci.c	2016-09-13 17:18:35.579259846 -0600
++++ b/drivers/ata/libahci.c	2016-07-27 20:25:34.217095567 -0600
+@@ -1826,7 +1826,7 @@ static irqreturn_t ahci_multi_irqs_intr(
+ 	return IRQ_WAKE_THREAD;
+ }
+ 
+-static irqreturn_t ahci_single_irq_intr(int irq, void *dev_instance)
++irqreturn_t ahci_single_irq_intr(int irq, void *dev_instance)
+ {
+ 	struct ata_host *host = dev_instance;
+ 	struct ahci_host_priv *hpriv;
+@@ -1885,6 +1885,7 @@ static irqreturn_t ahci_single_irq_intr(
+ 
+ 	return IRQ_RETVAL(handled);
+ }
++EXPORT_SYMBOL_GPL(ahci_single_irq_intr);
+ 
+ unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
+ {

src/patches/si5338_vsc330x.patch

+diff -Naur a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+--- a/drivers/clk/Kconfig	2016-01-25 18:31:43.413779725 -0700
++++ b/drivers/clk/Kconfig	2016-01-25 19:09:12.833821955 -0700
+@@ -59,6 +59,16 @@
+ 	  clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
+ 	  by control register.
+ 
++config COMMON_CLK_SI5338
++	tristate "Support Silicon Laboratories SI5338 Quad Clock Generator"
++	depends on I2C
++	select REGMAP_I2C
++	select RATIONAL
++	help
++	 Say Y here if you have a SI5338 Quad Clock Generator IC on the I2C bus.
++	 To compile this driver as a module, choose M here: the
++	 module will be called si5338.
++
+ config COMMON_CLK_SI5351
+ 	tristate "Clock driver for SiLabs 5351A/B/C"
+ 	depends on I2C
+diff -Naur a/drivers/clk/Makefile b/drivers/clk/Makefile
+--- a/drivers/clk/Makefile	2016-01-25 18:31:43.413779725 -0700
++++ b/drivers/clk/Makefile	2016-01-25 19:09:46.217822582 -0700
+@@ -35,6 +35,7 @@
+ obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
+ obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
+ obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
++obj-$(CONFIG_COMMON_CLK_SI5338)		+= clk-si5338.o
+ obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
+ obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o
+ obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o
+diff -Naur a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+--- a/drivers/misc/Kconfig	2016-01-28 19:14:34.610694113 -0700
++++ b/drivers/misc/Kconfig	2016-01-28 19:42:44.730725843 -0700
+@@ -515,6 +515,23 @@
+ 	  bus. System Configuration interface is one of the possible means
+ 	  of generating transactions on this bus.
+ 
++config VSC330X
++	tristate "Support VSC330X crosspoint switch"
++	help
++	  Say Y here if you have a VSC30X crosspoint switch IC on the I2C bus.
++	  To compile this driver as a module, choose M here: the
++	  module will be called vsc330x.
++
++config LTC3589
++	tristate "Support LTC3589 voltage regulator"
++	help
++	  Say Y here if you have a LTC3589 voltage regulator IC on the I2C bus.
++	  To compile this driver as a module, choose M here: the
++	  module will be called ltc3589. 
++	  Developed by Elphel, Inc.. 
++	  The default driver is found at drivers/regulator/ltc3589.c and 
++	  enabled with CONFIG_REGULATOR_LTC3589=y
++	  
+ config XILINX_TRAFGEN
+ 	tristate "Xilinx Traffic Generator"
+ 	depends on MICROBLAZE || ARCH_ZYNQ
+diff -Naur a/drivers/misc/Makefile b/drivers/misc/Makefile
+--- a/drivers/misc/Makefile	2016-01-28 19:14:34.610694113 -0700
++++ b/drivers/misc/Makefile	2016-01-28 19:19:56.638700159 -0700
+@@ -58,3 +58,5 @@
+ obj-$(CONFIG_ECHO)		+= echo/
+ obj-$(CONFIG_VEXPRESS_SYSCFG)	+= vexpress-syscfg.o
+ obj-$(CONFIG_CXL_BASE)		+= cxl/
++obj-$(CONFIG_VSC330X)	        += vsc330x.o
++obj-$(CONFIG_LTC3589)	        += ltc3589.o

src/patches/xilinx_emacps.c.patch

+diff -Naur a/drivers/net/ethernet/xilinx/xilinx_emacps.c b/drivers/net/ethernet/xilinx/xilinx_emacps.c
+--- a/drivers/net/ethernet/xilinx/xilinx_emacps.c	2016-01-25 18:34:24.065782741 -0700
++++ b/drivers/net/ethernet/xilinx/xilinx_emacps.c	2016-01-25 19:03:50.781815909 -0700
+@@ -479,6 +479,10 @@
+ #define XEMACPS_PTP_CC_MULT		(1 << 31)
+ #endif
+ 
++/* Elphel */
++#define AT803X_PHY_ID          0x004dd072 /*Particular one, AR8035 but we'll use a broad mask */
++#define AT803X_PHY_ID_MASK     0xffffffe0
++
+ #define xemacps_read(base, reg)						\
+ 	readl_relaxed(((void __iomem *)(base)) + (reg))
+ #define xemacps_write(base, reg, val)					\
+@@ -871,6 +875,49 @@
+ 	return 0;
+ }
+ 
++/* http://www.spinics.net/lists/devicetree/msg06322.html */
++static int ar8035_phy_fixup(struct phy_device *dev)
++{
++	u16 val;
++	struct net_local *lp = dev->bus->priv;
++	dev_dbg(&lp->pdev->dev,"fixup start");
++
++	/* Ar803x phy SmartEEE feature cause link status generates glitch,
++	* which cause ethernet link down/up issue, so disable SmartEEE
++	*/
++	phy_write(dev, 0xd, 0x3);
++	phy_write(dev, 0xe, 0x805d);
++	phy_write(dev, 0xd, 0x4003);
++
++	val = phy_read(dev, 0xe);
++	phy_write(dev, 0xe, val & ~(1 << 8));
++	/*Enable if needed */
++#if 0
++	/* To enable AR8031 output a 125MHz clk from CLK_25M */
++	phy_write(dev, 0xd, 0x7);
++	phy_write(dev, 0xe, 0x8016);
++	phy_write(dev, 0xd, 0x4007);
++
++	val = phy_read(dev, 0xe);
++	val &= 0xffe3;
++	val |= 0x18;
++	phy_write(dev, 0xe, val);
++#endif
++/* Next one what is really needed for Elphel 393 */
++	/* introduce tx clock delay */
++	phy_write(dev, 0x1d, 0x5);
++	val = phy_read(dev, 0x1e);
++	val |= 0x0100;
++	phy_write(dev, 0x1e, val);
++
++	/*check phy power*/
++	val = phy_read(dev, 0x0);
++	if (val & BMCR_PDOWN)
++		phy_write(dev, 0x0, val & ~BMCR_PDOWN);
++	dev_dbg(&lp->pdev->dev,"fixup end");
++	return 0;
++}
++
+ /**
+  * xemacps_mii_init - Initialize and register mii bus to network device
+  * @lp: local device instance pointer
+@@ -883,6 +930,8 @@
+ 	struct device_node *np = of_get_parent(lp->phy_node);
+ 	struct device_node *npp;
+ 
++	phy_register_fixup_for_uid(AT803X_PHY_ID,  AT803X_PHY_ID_MASK,  ar8035_phy_fixup);
++	
+ 	lp->mii_bus = of_mdio_find_bus(np);
+ 	if (!lp->has_mdio && lp->mii_bus)
+ 		return 0;

src/patches/xilinx_uartps.c.patch

+diff -Naur a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
+--- a/drivers/tty/serial/xilinx_uartps.c	2016-02-19 13:41:58.380680377 -0700
++++ b/drivers/tty/serial/xilinx_uartps.c	2016-02-19 13:47:50.776674338 -0700
+@@ -704,6 +704,9 @@
+ 	ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
+ 	cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
+ 
++	while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
++			(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
++		cpu_relax();
+ 	/*
+ 	 * Clear the RX disable and TX disable bits and then set the TX enable
+ 	 * bit and RX enable bit to enable the transmitter and receiver.