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Elphel
linux-elphel
Commits
222bb31e
Commit
222bb31e
authored
Mar 19, 2018
by
Oleg Dzhimiev
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Plain Diff
jpeg max fps testing
parent
b34fa5a2
Changes
3
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3 changed files
with
121 additions
and
29 deletions
+121
-29
mt9f002.c
src/drivers/elphel/mt9f002.c
+99
-23
mt9f002.h
src/drivers/elphel/mt9f002.h
+7
-5
pgm_functions.c
src/drivers/elphel/pgm_functions.c
+15
-1
No files found.
src/drivers/elphel/mt9f002.c
View file @
222bb31e
This diff is collapsed.
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src/drivers/elphel/mt9f002.h
View file @
222bb31e
...
...
@@ -21,7 +21,9 @@
#define MT9F002_I2C_ADDR 0x10 ///< MT9P I2C slave address (7 bit)
// bit 9 should have set masking for broken frames
#define MT9F002_RESET_REGISTER_VALUE 0x001c
// cleared bit 3 allows writing to some RO registers
//#define MT9F002_RESET_REGISTER_VALUE 0x001c
#define MT9F002_RESET_REGISTER_VALUE 0x0014
// number of lines to sacrifice before generating Frame Valid
#define MT9F002_VACT_DELAY 2
...
...
@@ -58,7 +60,8 @@
// Sensor clock dividers and multiplier
// These should be calculated based on the clocks above
// pll multiplier, default is 0xa5 (165), also tried 0xa2 (162)
// pll multiplier, default is 0xa5 (165) for 24MHz
// is set to 0xb4 (180) becuase clock is 22MHz (not 24)
#define MT9F002_PLL_MULTIPLIER_VALUE 0xb4
// pre_pll_clk_div (0x0304), default value is 0x6
#define MT9F002_PRE_PLL_CLK_DIV_VALUE 0x6
...
...
@@ -68,13 +71,12 @@
#define MT9F002_VT_SYS_CLK_DIV_VALUE 0x1
// shift_vt_pix_clk_div, default value is 0x1
#define MT9F002_SHIFT_VT_PIX_CLK_DIV 0x1
// op_pix_clk divider
#define MT9F002_OP_PIX_CLK_DIV 0xc
// Coarse Integration Time Margin
#define MT9F002_COARSE_EXPOS_MARGIN 0x1
/* ON Semi MT9F002 i2c register addresses */
/*
...
...
src/drivers/elphel/pgm_functions.c
View file @
222bb31e
...
...
@@ -512,7 +512,7 @@ int pgm_detectsensor (int sensor_port, ///< sensor port number (
// Freqs for sensors
if
((
thispars
->
pars
[
P_SENSOR
]
==
0
)
&&
((
sens
&
SENSOR_MASK
)
==
SENSOR_MT9F002
)){
setFramePar
(
sensor_port
,
thispars
,
P_CLK_SENSOR
,
24444000
);
setFramePar
(
sensor_port
,
thispars
,
P_CLK_SENSOR
,
MT9F002_VT_PIX_CLK
);
}
else
{
// this handles MT9x001 & MUX
setFramePar
(
sensor_port
,
thispars
,
P_CLK_SENSOR
,
48000000
);
...
...
@@ -1335,6 +1335,7 @@ int pgm_limitfps (int sensor_port, ///< sensor port number (0..3
if
(
min_period
!=
thispars
->
pars
[
P_PERIOD_MIN
])
{
SETFRAMEPARS_SET
(
P_PERIOD_MIN
,
min_period
);
// set it (and propagate to the later frames)
dev_dbg
(
g_dev_ptr
,
"{%d} SETFRAMEPARS_SET(P_PERIOD_MIN, 0x%x)
\n
"
,
sensor_port
,
min_period
);
pr_info
(
"{%d} min period got updated to 0x%x (clk_sensor=%d, clk_fpga=%d)
\n
"
,
sensor_port
,
min_period
,
clk_sensor
,
clk_fpga
);
MDP
(
DBGB_PADD
,
sensor_port
,
"SETFRAMEPARS_SET(P_PERIOD_MIN, 0x%x)
\n
"
,
min_period
)
}
if
(((
thispars
->
pars
[
P_FPSFLAGS
]
&
2
)
==
0
)
||
(
period
<
min_period
))
period
=
0x7fffffff
;
// no upper limit
...
...
@@ -2225,6 +2226,19 @@ int pgm_memcompressor (int sensor_port, ///< sensor port number (
(
cmprs_frame_format
.
num_macro_cols_m1
+
1
)
*
(
cmprs_frame_format
.
num_macro_rows_m1
+
1
)
);
pr_info
(
"PGM_MEMCOMPRESSOR: sport=%d width_bursts=%d width_marg=%d height_marg=%d num_macro_rows_m1=%d tile_width=%d tile_height=%d margin_left=%d margin_top=%d P_TILES=%d
\n
"
,
sensor_port
,
width_bursts
,
width_marg
,
height_marg
,
(
cmprs_frame_format
.
num_macro_rows_m1
+
1
)
<<
4
,
tile_width
,
tile_height
,
0
,
cmprs_top
,
(
cmprs_frame_format
.
num_macro_cols_m1
+
1
)
*
(
cmprs_frame_format
.
num_macro_rows_m1
+
1
)
);
setup_compressor_memory
(
sensor_port
,
// sensor port number (0..3)
width_bursts
,
// 13-bit - in 8*16=128 bit bursts
(
cmprs_frame_format
.
num_macro_rows_m1
+
1
)
<<
4
,
...
...
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