Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
L
linux-elphel
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
linux-elphel
Commits
135594fd
Commit
135594fd
authored
Mar 07, 2018
by
Oleg Dzhimiev
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
1. fixed i2caddr setting in device tree
parent
81559b1f
Changes
4
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
467 additions
and
22 deletions
+467
-22
mt9f002.c
src/drivers/elphel/mt9f002.c
+415
-7
mt9f002.h
src/drivers/elphel/mt9f002.h
+42
-5
mt9x001.c
src/drivers/elphel/mt9x001.c
+8
-8
sensor_common.h
src/drivers/elphel/sensor_common.h
+2
-2
No files found.
src/drivers/elphel/mt9f002.c
View file @
135594fd
This diff is collapsed.
Click to expand it.
src/drivers/elphel/mt9f002.h
View file @
135594fd
...
@@ -24,6 +24,38 @@
...
@@ -24,6 +24,38 @@
// number of lines to sacrifice before generating Frame Valid
// number of lines to sacrifice before generating Frame Valid
#define MT9F002_VACT_DELAY 2
#define MT9F002_VACT_DELAY 2
// Clocks, this is basis
// External sensor clock before pll
// Constant = 24.444MHz in Hz
#define MT9F002_EXT_CLK 24444000
// Virtual pixel clock is used as the basis for frame timing equations.
// Constant = 244.44MHz in Hz
#define MT9F002_VT_PIX_CLK 244440000
// Serial output clock
// Constant = 733.32MHz in Hz
#define MT9F002_OP_SYS_CLK 733320000
// Sensor clock dividers and multiplier
// These should be calculated based on the clocks above
// pll multiplier
#define MT9F002_PLL_MULTIPLIER_VALUE 0xb4
// pre_pll_clk_div (0x0304), default value is 0x6
#define MT9F002_PRE_PLL_CLK_DIV_VALUE 0x6
// vt_pix_clk_div (0x0300), default value is 0x6
#define MT9F002_VT_PIX_CLK_DIV_VALUE 0x6
// vt_sys_clk_div (0x0300), default value is 0x6
#define MT9F002_VT_SYS_CLK_DIV_VALUE 0x1
// shift_vt_pix_clk_div, default value is 0x1
#define MT9F002_SHIFT_VT_PIX_CLK_DIV 0x1
// Coarse Integration Time Margin
#define MT9F002_COARSE_EXPOS_MARGIN 0x1
/* ON Semi MT9F002 i2c register addresses */
/* ON Semi MT9F002 i2c register addresses */
/*
/*
...
@@ -559,14 +591,19 @@
...
@@ -559,14 +591,19 @@
#define P_MT9F002_ANALOG_GAIN_CODE_GLOBAL 16
#define P_MT9F002_ANALOG_GAIN_CODE_GLOBAL 16
#define P_MT9F002_ANALOG_GAIN_CODE_RED 17
#define P_MT9F002_ANALOG_GAIN_CODE_RED 17
#define P_MT9F002_ANALOG_GAIN_CODE_BLUE 18
#define P_MT9F002_ANALOG_GAIN_CODE_BLUE 18
#define P_MT9F002_COARSE_INTEGRATION_TIME 19
#define P_MT9F002_COARSE_INTEGRATION_TIME 19
#define P_MT9F002_FINE_INTEGRATION_TIME 20
#define P_MT9F002_Y_ADDR_START 20
#define P_MT9F002_Y_ADDR_START 21
#define P_MT9F002_Y_ADDR_END 21
#define P_MT9F002_Y_ADDR_END 22
#define P_MT9F002_X_ADDR_START 22
#define P_MT9F002_Y_OUTPUT_SIZE 23
#define P_MT9F002_X_ADDR_END 23
#define P_MT9F002_X_ADDR_START 24
#define P_MT9F002_X_ADDR_END 25
#define P_MT9F002_X_OUTPUT_SIZE 26
#define P_MT9F002_LINE_LENGTH_PCK 27
#define P_MT9F002_READ_MODE 2
4
#define P_MT9F002_READ_MODE 2
8
//#define P_REG(x) x
//#define P_REG(x) x
...
...
src/drivers/elphel/mt9x001.c
View file @
135594fd
...
@@ -800,6 +800,14 @@ int mt9x001_pgm_detectsensor (int sensor_port, ///< sensor port
...
@@ -800,6 +800,14 @@ int mt9x001_pgm_detectsensor (int sensor_port, ///< sensor port
// try MT9P001 first
// try MT9P001 first
psensor
=
&
mt9p001
;
psensor
=
&
mt9p001
;
// temporary solution
pcfg
=
&
pSensorPortConfig
[
sensor_port
];
name
=
get_name_by_code
(
pcfg
->
sensor
[
0
],
DETECT_SENSOR
);
dc
=
xi2c_dev_get
(
name
);
if
(
dc
){
psensor
->
i2c_addr
=
dc
->
slave7
;
}
// set control lines
// set control lines
sensio_ctl
.
mrst
=
1
;
sensio_ctl
.
mrst
=
1
;
sensio_ctl
.
mrst_set
=
1
;
sensio_ctl
.
mrst_set
=
1
;
...
@@ -848,14 +856,6 @@ int mt9x001_pgm_detectsensor (int sensor_port, ///< sensor port
...
@@ -848,14 +856,6 @@ int mt9x001_pgm_detectsensor (int sensor_port, ///< sensor port
// MDD1(dev_dbg(g_dev_ptr,"sensor=0x%x, sensor_subtype=0x%x\n", (int)sensor, (int)sensor_subtype));
// MDD1(dev_dbg(g_dev_ptr,"sensor=0x%x, sensor_subtype=0x%x\n", (int)sensor, (int)sensor_subtype));
if
(
sensor_subtype
==
0
)
return
0
;
// no sensor found
if
(
sensor_subtype
==
0
)
return
0
;
// no sensor found
// temporary solution
pcfg
=
&
pSensorPortConfig
[
sensor_port
];
name
=
get_name_by_code
(
pcfg
->
sensor
[
0
],
DETECT_SENSOR
);
dc
=
xi2c_dev_get
(
name
);
if
(
dc
){
psensor
->
i2c_addr
=
dc
->
slave7
;
}
// Sensor recognized, go on
// Sensor recognized, go on
// memcpy(&sensor, psensor, sizeof(mt9p001)); // copy sensor definitions
// memcpy(&sensor, psensor, sizeof(mt9p001)); // copy sensor definitions
memcpy
(
sensor
,
psensor
,
sizeof
(
mt9p001
));
// copy sensor definitions
memcpy
(
sensor
,
psensor
,
sizeof
(
mt9p001
));
// copy sensor definitions
...
...
src/drivers/elphel/sensor_common.h
View file @
135594fd
...
@@ -128,7 +128,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
...
@@ -128,7 +128,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
#define X3X3_I2C_SEND2_LUT(port,frame,si,reg,data) {\
#define X3X3_I2C_SEND2_LUT(port,frame,si,reg,data) {\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[(si)][((reg)>>8)&0xff];\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[(si)][((reg)>>8)&0xff];\
BUG_ON(
!(_PAGE&0xffffff00)
);\
BUG_ON(
_PAGE&0xffffff00
);\
write_xi2c_reg16_abs_asap((port),_PAGE,(frame),(reg)&0xff,(data));\
write_xi2c_reg16_abs_asap((port),_PAGE,(frame),(reg)&0xff,(data));\
}
}
...
@@ -157,7 +157,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
...
@@ -157,7 +157,7 @@ long long get_frame_pos(unsigned int chn, unsigned int pos);
* @param data value to set (16 bits) */
* @param data value to set (16 bits) */
#define X3X3_I2C_SEND2_LUT_ASAP(port,si,reg,data) {\
#define X3X3_I2C_SEND2_LUT_ASAP(port,si,reg,data) {\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[(si)][((reg)>>8)&0xff];\
int _PAGE = pSensorPortConfig[(port)].haddr2rec[(si)][((reg)>>8)&0xff];\
BUG_ON(
!(_PAGE&0xffffff00)
);\
BUG_ON(
_PAGE&0xffffff00
);\
write_xi2c_reg16((port),_PAGE,(reg)&0xff,(data));\
write_xi2c_reg16((port),_PAGE,(reg)&0xff,(data));\
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment