Commit 0adf97eb authored by Andrey Filippov's avatar Andrey Filippov

debugging cache coherency

parent 0a0a3e4a
......@@ -124,7 +124,7 @@
/**
* \def MDF21(x) optional debug output
*/
#define ELPHEL_INFO 1
// #define ELPHEL_INFO 1
#if ELPHEL_DEBUG
// only when commands are issued
#define MDF21(x) { if (GLOBALPARS(G_DEBUG) & (1 <<21)) {printk("%s:%d:%s ",__FILE__,__LINE__,__FUNCTION__);x ;} }
......@@ -460,7 +460,8 @@ int set_histograms (int sensor_port, ///< sensor port number (0..3)
/// __cpuc_flush_dcache_area(pElphel_buf->histograms_vaddr, pElphel_buf->histograms_size);
/// outer_inv_range(fpga_hist_phys, fpga_hist_phys + pElphel_buf->histograms_size * PAGE_SIZE); // END - EXCLUSIVE!, CHANGE ORDER (AFTER ____cpuc_flush_dcache_area
/// TODO: Cleanup, something is still wrong with caching. test with
/// http://192.168.0.45/pnghist.cgi?sensor_port=0&sqrt=1&scale=5&average=5&height=128&fillz=1&linterpz=0&draw=2&colors=41&debug=9
for (i=0; i<4; i++) if (needed & ( 1 << i )) {
u32 phys_addr= fpga_hist_phys + PAGE_SIZE*(hist_frame + PARS_FRAMES * (sensor_chn + MAX_SENSORS *sensor_port)) + i*256*sizeof(u32); // start of selected color
u32 * dma_data = &fpga_hist_data[sensor_port][sensor_chn][hist_frame][i][0];
......
......@@ -57,7 +57,8 @@
#include "cci2c.h"
#include <uapi/elphel/x393_devices.h>
//#define DEBUG_CACHE
//#define DEBUG_CACHE_VALUE 0xa5
#if 1
#define D(x) x
//#define D0(x) x
......@@ -75,6 +76,7 @@
//#define D1(x) x
#define IS_103695_REV_A 1
#define MULT_SAXI_CHN 0 ///< using channel 0 of a 4-channel DMA engine
......@@ -87,7 +89,7 @@
#define LOGGER_USE_IRQ 1
//#define LOGGER_MIN_BYTES_AHEAD 128 // actual 64, but got some zeros, let's wait extra 64-byte record
#define LOGGER_MIN_BYTES_AHEAD 256 // actual 64, but got some zeros, let's wait extra 64-byte record // with 128 was still getting 32x0?
#define LOGGER_MIN_BYTES_AHEAD 64 // 256 // actual 64, but got some zeros, let's wait extra 64-byte record // with 128 was still getting 32x0?
#ifdef NC353
#define EXT_DMA_1_START \
do { reg_bif_dma_rw_ch1_start c = {.run=1};\
......@@ -416,6 +418,12 @@ static void set_logger_params(int which){ // 1 - program IOPINS, 2 - reset first
dev_info(g_dev_ptr,"Stopping DMA\n");
dev_dbg(g_dev_ptr,"Stopping DMA\n");
logger_dma_stop();
#ifdef DEBUG_CACHE
outer_inv_range(logger_phys, logger_phys + logger_size);
__cpuc_flush_dcache_area(logger_buffer, logger_size);
memset(logger_buffer, DEBUG_CACHE_VALUE, logger_size);
#endif
}
#ifdef NC353
......@@ -773,15 +781,17 @@ static int imu_open(struct inode *inode, struct file *filp) {
set_logger_params(WHICH_INIT |
WHICH_RESET |
WHICH_RESET_SPI |
/*
WHICH_DIVISOR |
WHICH_RS232DIV |
WHICH_NMEA |
WHICH_CONFIG |
WHICH_REGISTERS |
WHICH_MESSAGE |
*/
WHICH_PERIOD |
WHICH_EN_DMA |
WHICH_CAMSYNC |
// WHICH_CAMSYNC |
WHICH_EN_LOGGER );
numBytesRead=0;
} else {
......@@ -821,6 +831,14 @@ static int imu_release(struct inode *inode, struct file *filp) {
int p = MINOR(inode->i_rdev);
switch ( p ) {
case DEV393_MINOR(DEV393_LOGGER) :
#ifdef DEBUG_CACHE
dev_dbg(g_dev_ptr,"got LSEEK_IMU_STOP\n");
set_logger_params(WHICH_RESET | WHICH_RESET_SPI);
numBytesRead=0;
dev_info(g_dev_ptr,"Closing IMU device in debug mode. Stopping DMA\n");
dev_dbg(g_dev_ptr,"Closing IMU device in debug mode. Stopping DMA\n");
break;
#endif
case DEV393_MINOR(DEV393_LOGGER_CTRL):
dev_info(g_dev_ptr,"Closing IMU device, numBytesWritten=0x%llx, numBytesRead=0x%llx (only global pointer, does not include files opened in read mode)\n", numBytesWritten, numBytesRead);
dev_dbg(g_dev_ptr,"Closing IMU device, numBytesWritten=0x%llx, numBytesRead=0x%llx (only global pointer, does not include files opened in read mode)\n", numBytesWritten, numBytesRead);
......@@ -1046,6 +1064,9 @@ static ssize_t imu_read(struct file * file, char * buf, size_t count, loff_t *of
if (pe > logger_size) pe= logger_size;
#endif
/// copy all (or first part)
/// invalidate CPU L1 and L2 caches (in this order)
outer_inv_range(logger_phys + byteIndexRead, logger_phys + pe);
__cpuc_flush_dcache_area(&charDMABuf[byteIndexRead], (pe-byteIndexRead)); // L2_INVAL_SIZE);
err=copy_to_user(buf, &charDMABuf[byteIndexRead], (pe-byteIndexRead));
if (err) {
dev_err(g_dev_ptr,"1. tried to copy 0x%x bytes from offset 0x%llx, result=0x%x\n", (pe-byteIndexRead), *off,err);
......@@ -1058,7 +1079,9 @@ static ssize_t imu_read(struct file * file, char * buf, size_t count, loff_t *of
dev_dbg(g_dev_ptr,"leftToRead=0x%08x thisNumBytesRead=0x%08x\n", leftToRead, (int) thisNumBytesRead);
///Do we need to copy from the beginning of the buffer?
if (leftToRead>0) {
// err=copy_to_user(buf, &charDMABuf[0], leftToRead);
/// invalidate CPU L1 and L2 caches (in this order)
outer_inv_range(logger_phys, logger_phys + leftToRead);
__cpuc_flush_dcache_area(&charDMABuf[0], leftToRead); // L2_INVAL_SIZE);
err=copy_to_user(&buf[pe-byteIndexRead], &charDMABuf[0], leftToRead);
byteIndexRead=0;
}
......@@ -1097,7 +1120,7 @@ static irqreturn_t logger_irq_handler(int irq, ///< [in] interrupt number
void *dev_id) ///< [in] pointer to driver's private data structure
///< @return \e IRQ_HANDLED if interrupt was processed and \e IRQ_NONE otherwise
{
x393_mult_saxi_al_t mult_saxi_dwp = x393_mult_saxi_pointers(MULT_SAXI_CHN);
x393_mult_saxi_al_t volatile mult_saxi_dwp = x393_mult_saxi_pointers(MULT_SAXI_CHN);
if (mult_saxi_dwp.addr32 < logger_offs32){
numBytesWrittenBase += logger_size;
}
......
......@@ -752,10 +752,11 @@ void tasklet_compressor_function(unsigned long arg)
outer_inv_range(phys_addr_start, phys_addr_end);
__cpuc_flush_dcache_area(virt_addr_start, L2_INVAL_SIZE);
} else {
// from pointer to the end of buffer
phys_addr_end = phys_addr_start + (ccam_dma_size - DW2BYTE(jptr->fpga_cntr_prev) - 1);
outer_inv_range(phys_addr_start, phys_addr_end);
__cpuc_flush_dcache_area(virt_addr_start, ccam_dma_size - DW2BYTE(jptr->fpga_cntr_prev));
// wrapped-over part in the beginning of the buffer
phys_addr_start = circbuf_priv_ptr[jptr->chn_num].phys_addr;
phys_addr_end = phys_addr_start + (sz - ccam_dma_size - 1);
virt_addr_start = circbuf_priv_ptr[jptr->chn_num].buf_ptr;
......
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