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jean-pierre charras authored
Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy. Known bug in intermediate netlist generation: multi parts per package have their common pins listed more than once in nets section. Will be fixed.
0cb6cd8c
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sonde xilinx-cache.lib | ||
sonde xilinx.brd | ||
sonde xilinx.cmp | ||
sonde xilinx.drl | ||
sonde xilinx.net | ||
sonde xilinx.pro | ||
sonde xilinx.sch |