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Commit fde42439 authored by jean-pierre charras's avatar jean-pierre charras
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Fixes

parent 38a3f1b8
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Showing with 316 additions and 427 deletions
demos/flat_hierarchy/flat_hierarchy.pro
View file @ fde42439
update=18/4/2006-09:31:05 update=07/03/2011 07:10:44
last_client=pcbnew last_client=cvpcb
[general] [general]
version=1 version=1
RootSch=pic_programmer.sch RootSch=pic_programmer.sch
BoardNm=pic_programmer.brd BoardNm=pic_programmer.brd
[cvpcb] [common]
version=1 NetDir=
NetITyp=0 [pcbnew]
NetIExt=.net version=1
PkgIExt=.pkg PadDril=400
NetType=0 PadDimH=700
[cvpcb/libraries] PadDimV=700
EquName1=devcms PadForm=1
[common] PadMask=14745599
NetDir= ViaDiam=650
[pcbnew] ViaDril=250
version=1 Isol=100
PadDril=400 Countlayer=2
PadDimH=700 Lpiste=250
PadDimV=700 RouteTo=15
PadForm=1 RouteBo=0
PadMask=14745599 TypeVia=3
ViaDiam=650 Segm45=1
ViaDril=250 Racc45=1
Isol=100 Unite=0
Countlayer=2 SegFill=1
Lpiste=250 SegAffG=0
RouteTo=15 NewAffG=1
RouteBo=0 PadFill=1
TypeVia=3 PadAffG=1
Segm45=1 PadSNum=1
Racc45=1 ModAffC=1
Unite=0 ModAffT=1
SegFill=1 PcbAffT=1
SegAffG=0 SgPcb45=1
NewAffG=1 TxtPcbV=800
PadFill=1 TxtPcbH=600
PadAffG=1 TxtModV=600
PadSNum=1 TxtModH=600
ModAffC=1 TxtModW=120
ModAffT=1 HPGLnum=1
PcbAffT=1 HPGdiam=15
SgPcb45=1 HPGLSpd=20
TxtPcbV=800 HPGLrec=2
TxtPcbH=600 HPGLorg=0
TxtModV=600 GERBmin=15
TxtModH=600 VEgarde=100
TxtModW=120 DrawLar=150
HPGLnum=1 EdgeLar=150
HPGdiam=15 TxtLar=120
HPGLSpd=20 MSegLar=150
HPGLrec=2 ForPlot=1
HPGLorg=0 WpenSer=10
GERBmin=15 UserGrX=0,01
VEgarde=100 UserGrY=0,01
DrawLar=150 UserGrU=1
EdgeLar=150 DivGrPc=1
TxtLar=120 TimeOut=600
MSegLar=150 MaxLnkS=3
ForPlot=1 ShowRat=0
WpenSer=10 ShowMRa=1
UserGrX=0,01 [pcbnew/libraries]
UserGrY=0,01 LibName1=connect
UserGrU=1 LibName2=discret
DivGrPc=1 LibName3=pin_array
TimeOut=600 LibName4=divers
MaxLnkS=3 LibName5=libcms
ShowRat=0 LibName6=display
ShowMRa=1 LibName7=dip_sockets
[pcbnew/libraries] LibDir=
LibDir= [cvpcb]
LibName1=supports version=1
LibName2=connect NetIExt=.net
LibName3=discret [cvpcb/libraries]
LibName4=pin_array EquName1=devcms
LibName5=divers
LibName6=libcms
LibName7=display
demos/interf_u/interf_u.pro
View file @ fde42439
update=17/02/2011 19:46:34 update=07/03/2011 19:57:09
version=1 version=1
last_client=pcbnew last_client=pcbnew
[common] [common]
...@@ -55,13 +55,13 @@ LibName8=adc-dac ...@@ -55,13 +55,13 @@ LibName8=adc-dac
LibName9=memory LibName9=memory
LibName10=xilinx LibName10=xilinx
LibName11=special LibName11=special
LibName12=image
[pcbnew] [pcbnew]
version=1 version=1
PadDrlX=354 PadDrlX=354
PadDimH=550 PadDimH=550
PadDimV=550 PadDimV=550
BoardThickness=630 BoardThickness=630
SgPcb45=1
TxtPcbV=800 TxtPcbV=800
TxtPcbH=600 TxtPcbH=600
TxtModV=600 TxtModV=600
...@@ -71,10 +71,10 @@ VEgarde=100 ...@@ -71,10 +71,10 @@ VEgarde=100
DrawLar=150 DrawLar=150
EdgeLar=50 EdgeLar=50
TxtLar=170 TxtLar=170
MSegLar=400 MSegLar=150
LastNetListRead=interf_u.net LastNetListRead=..\\pic_programmer\\pic_programmer.net
[pcbnew/libraries] [pcbnew/libraries]
LibDir=F:\\kicad\\share\\modules\\packages3d LibDir=
LibName1=connect LibName1=connect
LibName2=discret LibName2=discret
LibName3=dip_sockets LibName3=dip_sockets
......
demos/sonde xilinx/sonde xilinx.drl deleted 100644 → 0
View file @ 38a3f1b8
M48
;DRILL file {PCBNEW (2007-04-24)} date 2/5/2007-08:54:51
;FORMAT={2:4 / absolute / Pouces / Format décimal}
R,T
VER,1
FMAT,2
INCH,TZ
TCST,OFF
ICI,OFF
ATC,ON
T1C0.002
T2C0.025
T3C0.032
T4C0.060
%
M47
G05
M72
T1
X4.050Y2.650
X4.050Y4.350
X7.250Y4.350
X7.250Y2.650
T2
X7.000Y3.200
X4.900Y3.450
X5.475Y3.950
T3
X5.400Y2.850
X5.800Y2.850
X4.800Y3.000
X4.400Y3.000
X6.400Y3.500
X6.000Y3.500
X5.950Y2.900
X6.350Y2.900
X4.800Y3.300
X4.400Y3.300
X4.800Y3.650
X4.400Y3.650
X4.800Y3.400
X4.400Y3.400
X4.800Y3.200
X4.400Y3.200
X4.800Y3.100
X4.400Y3.100
X6.400Y3.700
X6.000Y3.700
X6.400Y3.900
X6.000Y3.900
X6.400Y4.150
X6.000Y4.150
X4.800Y4.100
X4.400Y4.100
X5.300Y3.000
X5.800Y3.000
X6.000Y3.100
X6.300Y3.100
X5.000Y2.850
X5.300Y2.850
X5.550Y3.250
X5.550Y3.350
X5.550Y3.450
X5.550Y3.550
X5.550Y3.650
X5.550Y3.750
X5.550Y3.850
X5.850Y3.850
X5.850Y3.750
X5.850Y3.650
X5.850Y3.550
X5.850Y3.450
X5.850Y3.350
X5.850Y3.250
X5.000Y3.250
X5.000Y3.350
X5.000Y3.450
X5.000Y3.550
X5.000Y3.650
X5.000Y3.750
X5.000Y3.850
X5.300Y3.850
X5.300Y3.750
X5.300Y3.650
X5.300Y3.550
X5.300Y3.450
X5.300Y3.350
X5.300Y3.250
X5.550Y4.050
X5.550Y4.250
X5.950Y2.750
X6.150Y2.750
X5.700Y4.050
X5.700Y4.250
X5.850Y4.050
X5.850Y4.250
T4
X6.700Y3.200
X6.700Y3.400
X6.700Y3.000
X6.700Y3.600
X6.700Y3.800
X6.700Y4.000
T0
M30
demos/sonde xilinx/sonde xilinx.pro
View file @ fde42439
update=27/05/2010 12:18:31 update=07/03/2011 09:04:59
version=1 version=1
last_client=pcbnew last_client=pcbnew
[cvpcb] [cvpcb]
...@@ -77,7 +77,6 @@ PadDrlX=320 ...@@ -77,7 +77,6 @@ PadDrlX=320
PadDimH=620 PadDimH=620
PadDimV=900 PadDimV=900
BoardThickness=630 BoardThickness=630
SgPcb45=1
TxtPcbV=600 TxtPcbV=600
TxtPcbH=600 TxtPcbH=600
TxtModV=600 TxtModV=600
...@@ -88,7 +87,7 @@ DrawLar=120 ...@@ -88,7 +87,7 @@ DrawLar=120
EdgeLar=120 EdgeLar=120
TxtLar=120 TxtLar=120
MSegLar=120 MSegLar=120
LastNetListRead= LastNetListRead=sonde xilinx.net
[pcbnew/libraries] [pcbnew/libraries]
LibDir= LibDir=
LibName1=supports LibName1=supports
......
demos/test_xil_95108/carte_test.pro
View file @ fde42439
update=10/5/2004-12:26:41 update=07/03/2011 07:11:33
version=1 version=1
last_client=kicad last_client=cvpcb
[pcbnew] [pcbnew]
version=1 version=1
LibDir= LibDir=
Sel_Mod=1 Sel_Mod=1
NetType=0 NetType=0
PadDril=320 PadDril=320
PadDimH=550 PadDimH=550
PadDimV=550 PadDimV=550
PadOfDH=0 PadOfDH=0
PadOfDV=0 PadOfDV=0
PadForm=1 PadForm=1
PadMask=14745599 PadMask=14745599
PadAttr=0 PadAttr=0
PadOrie=0 PadOrie=0
ViaDiam=450 ViaDiam=450
ViaDril=250 ViaDril=250
Isol=100 Isol=100
Mlayer=536838151 Mlayer=536838151
Lpiste=250 Lpiste=250
RouteTo=15 RouteTo=15
RouteBo=0 RouteBo=0
TypeVia=3 TypeVia=3
Segm45=1 Segm45=1
Racc45=1 Racc45=1
Unite=0 Unite=0
SegFill=1 SegFill=1
SegAffG=0 SegAffG=0
NewAffG=1 NewAffG=1
PadFill=1 PadFill=1
PadAffG=1 PadAffG=1
PadSNum=1 PadSNum=1
ModAffC=0 ModAffC=0
ModAffT=0 ModAffT=0
PcbAffT=0 PcbAffT=0
SgPcb45=1 SgPcb45=1
TxtPcbV=600 TxtPcbV=600
TxtPcbH=600 TxtPcbH=600
GridX=500 GridX=500
GridY=500 GridY=500
TxtModV=500 TxtModV=500
TxtModH=500 TxtModH=500
TxtModW=80 TxtModW=80
HPGLnum=1 HPGLnum=1
Pltmarg=300 Pltmarg=300
HPGdiam=15 HPGdiam=15
HPGLSpd=20 HPGLSpd=20
HPGLrec=2 HPGLrec=2
HPGLorg=0 HPGLorg=0
GERBmin=15 GERBmin=15
GERBfmt=1 GERBfmt=1
VEgarde=100 VEgarde=100
DrawLar=120 DrawLar=120
EdgeLar=120 EdgeLar=120
TxtLar=80 TxtLar=80
MSegLar=120 MSegLar=120
ForPlot=1 ForPlot=1
WpenSer=10 WpenSer=10
UserGrX=500 UserGrX=500
UserGrY=500 UserGrY=500
UserGrU=1 UserGrU=1
DivGrPc=1 DivGrPc=1
TimeOut=600 TimeOut=600
ShowRat=0 ShowRat=0
ShowMRa=0 ShowMRa=0
[pcbnew/libraries] [pcbnew/libraries]
LibName1=supports LibName1=connect
LibName2=connect LibName2=discret
LibName3=discret LibName3=pin_array
LibName4=pin_array LibName4=divers
LibName5=divers LibName5=libcms
LibName6=libcms LibName6=dip_sockets
[cvpcb] LibDir=
version=1 [eeschema]
NetITyp=0 version=1
NetIExt=.net LibDir=
PkgIExt=.pkg NetFmt=1
NetDir= HPGLSpd=20
LibDir= HPGLDm=15
NetType=0 HPGLNum=1
[cvpcb/libraries] offX_A4=0
EquName1=devcms offY_A4=0
[eeschema] offX_A3=0
version=1 offY_A3=0
LibDir= offX_A2=0
NetFmt=1 offY_A2=0
HPGLSpd=20 offX_A1=0
HPGLDm=15 offY_A1=0
HPGLNum=1 offX_A0=0
offX_A4=0 offY_A0=0
offY_A4=0 offX_A=0
offX_A3=0 offY_A=0
offY_A3=0 offX_B=0
offX_A2=0 offY_B=0
offY_A2=0 offX_C=0
offX_A1=0 offY_C=0
offY_A1=0 offX_D=0
offX_A0=0 offY_D=0
offY_A0=0 offX_E=0
offX_A=0 offY_E=0
offY_A=0 RptD_X=0
offX_B=0 RptD_Y=100
offY_B=0 RptLab=1
offX_C=0 PenMin=20
offY_C=0 SimCmd=
offX_D=0 UseNetN=0
offY_D=0 [eeschema/Libraries]
offX_E=0 LibName1=power
offY_E=0 LibName2=device
RptD_X=0 LibName3=linear
RptD_Y=100 LibName4=regul
RptLab=1 LibName5=74xx
PenMin=20 LibName6=cmos4000
SimCmd= LibName7=adc-dac
UseNetN=0 LibName8=memory
[eeschema/Libraries] LibName9=xilinx
LibName1=power LibName10=special
LibName2=device LibName11=analog_switches
LibName3=linear [general]
LibName4=regul version=1
LibName5=74xx RootSch=carte_test.sch
LibName6=cmos4000 BoardNm=carte_test.brd
LibName7=adc-dac [cvpcb]
LibName8=memory version=1
LibName9=xilinx NetIExt=.net
LibName10=special [cvpcb/libraries]
LibName11=analog_switches EquName1=devcms
[general]
version=1
RootSch=carte_test.sch
BoardNm=carte_test.brd
demos/video/video.pro
View file @ fde42439
update=04/12/2010 17:34:26 update=jeu. 03 mars 2011 20:58:32 CET
version=1 version=1
last_client=pcbnew last_client=pcbnew
[general] [general]
version=1 version=1
RootSch=video.sch RootSch=video.sch
BoardNm=video.brd BoardNm=video.brd
[cvpcb] [cvpcb]
version=1 version=1
NetIExt=net NetIExt=net
[cvpcb/libraries] [cvpcb/libraries]
EquName1=devcms EquName1=devcms
[eeschema] [eeschema]
version=1 version=1
LibDir= LibDir=
NetFmt=1 NetFmt=1
HPGLSpd=20 HPGLSpd=20
HPGLDm=15 HPGLDm=15
HPGLNum=1 HPGLNum=1
offX_A4=0 offX_A4=0
offY_A4=0 offY_A4=0
offX_A3=0 offX_A3=0
offY_A3=0 offY_A3=0
offX_A2=0 offX_A2=0
offY_A2=0 offY_A2=0
offX_A1=0 offX_A1=0
offY_A1=0 offY_A1=0
offX_A0=0 offX_A0=0
offY_A0=0 offY_A0=0
offX_A=0 offX_A=0
offY_A=0 offY_A=0
offX_B=0 offX_B=0
offY_B=0 offY_B=0
offX_C=0 offX_C=0
offY_C=0 offY_C=0
offX_D=0 offX_D=0
offY_D=0 offY_D=0
offX_E=0 offX_E=0
offY_E=0 offY_E=0
RptD_X=0 RptD_X=0
RptD_Y=100 RptD_Y=100
RptLab=1 RptLab=1
LabSize=60 LabSize=60
PrintMonochrome=1 PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1 ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries] [eeschema/libraries]
LibName1=power LibName1=power
LibName2=device LibName2=device
LibName3=transistors LibName3=transistors
LibName4=conn LibName4=conn
LibName5=linear LibName5=linear
LibName6=regul LibName6=regul
LibName7=74xx LibName7=74xx
LibName8=cmos4000 LibName8=cmos4000
LibName9=adc-dac LibName9=adc-dac
LibName10=memory LibName10=memory
LibName11=xilinx LibName11=xilinx
LibName12=special LibName12=special
LibName13=microcontrollers LibName13=microcontrollers
LibName14=dsp LibName14=dsp
LibName15=microchip LibName15=microchip
LibName16=analog_switches LibName16=analog_switches
LibName17=motorola LibName17=motorola
LibName18=texas LibName18=texas
LibName19=intel LibName19=intel
LibName20=audio LibName20=audio
LibName21=interface LibName21=interface
LibName22=digital-audio LibName22=digital-audio
LibName23=philips LibName23=philips
LibName24=display LibName24=display
LibName25=cypress LibName25=cypress
LibName26=siliconi LibName26=siliconi
LibName27=opto LibName27=opto
LibName28=atmel LibName28=atmel
LibName29=contrib LibName29=contrib
LibName30=valves LibName30=valves
[pcbnew] [pcbnew]
version=1 version=1
PadDrlX=1200 PadDrlX=1200
PadDimH=1500 PadDimH=1500
PadDimV=2000 PadDimV=2000
BoardThickness=630 BoardThickness=630
SgPcb45=1 TxtPcbV=600
TxtPcbV=600 TxtPcbH=600
TxtPcbH=600 TxtModV=500
TxtModV=500 TxtModH=500
TxtModH=500 TxtModW=80
TxtModW=80 VEgarde=100
VEgarde=100 DrawLar=120
DrawLar=120 EdgeLar=80
EdgeLar=80 TxtLar=80
TxtLar=80 MSegLar=120
MSegLar=120 LastNetListRead=video.net
LastNetListRead=video.net [pcbnew/libraries]
[pcbnew/libraries] LibDir=
LibDir= LibName1=dip_sockets
LibName1=dip_sockets LibName2=connect
LibName2=connect LibName3=discret
LibName3=discret LibName4=pin_array
LibName4=pin_array LibName5=divers
LibName5=divers LibName6=libcms
LibName6=libcms
pcbnew/tool_pcb.cpp
View file @ fde42439
...@@ -686,6 +686,9 @@ void PCB_EDIT_FRAME::updateDesignRulesSelectBoxes() ...@@ -686,6 +686,9 @@ void PCB_EDIT_FRAME::updateDesignRulesSelectBoxes()
m_ClearanceBox->Clear(); m_ClearanceBox->Clear();
m_ClearanceBox->AppendText( msg ); m_ClearanceBox->AppendText( msg );
} }
updateTraceWidthSelectBox();
updateViaSizeSelectBox();
} }
......
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