Loading pcbnew/class_board.cpp +11 −12 Original line number Diff line number Diff line Loading @@ -594,10 +594,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, int aControl ) case TYPE_TRACK: case TYPE_VIA: { TRACK* insertAid = ( (TRACK*) aBoardItem )->GetBestInsertPoint( this ); TRACK* insertAid; insertAid = ( (TRACK*) aBoardItem )->GetBestInsertPoint( this ); m_Track.Insert( (TRACK*) aBoardItem, insertAid ); } break; case TYPE_ZONE: Loading pcbnew/class_track.cpp +0 −6 Original line number Diff line number Diff line Loading @@ -492,12 +492,6 @@ void SEGVIA::ReturnLayerPair( int* top_layer, int* bottom_layer ) const } /* * Function GetBestInsertPoint * Search the "best" insertion point within the track linked list * the best point is the of the corresponding net code section * return the item found in the linked list (or NULL if no track) */ TRACK* TRACK::GetBestInsertPoint( BOARD* aPcb ) { TRACK* track; Loading pcbnew/class_zone.cpp +10 −4 Original line number Diff line number Diff line Loading @@ -943,13 +943,19 @@ bool ZONE_CONTAINER::HitTest( EDA_RECT& refArea ) int ZONE_CONTAINER::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const { NETCLASS* myclass = GetNetClass(); int myClearance = m_ZoneClearance; #if 0 // maybe the netclass clearance should not come into play for a zone? #if 0 // Maybe the netclass clearance should not come into play for a zone? // At least the policy decision can be controlled by the zone // itself, i.e. here. On reasons of insufficient documentation, // the user will be less bewildered if we simply respect the // "zone clearance" setting in the zone properties dialog. (At least // until there is a UI boolean for this.) if( myclass ) myClearance = max( myClearance, myclass->GetClearance() ); NETCLASS* myClass = GetNetClass(); if( myClass ) myClearance = std::max( myClearance, myClass->GetClearance() ); #endif if( aItem ) Loading Loading
pcbnew/class_board.cpp +11 −12 Original line number Diff line number Diff line Loading @@ -594,10 +594,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, int aControl ) case TYPE_TRACK: case TYPE_VIA: { TRACK* insertAid = ( (TRACK*) aBoardItem )->GetBestInsertPoint( this ); TRACK* insertAid; insertAid = ( (TRACK*) aBoardItem )->GetBestInsertPoint( this ); m_Track.Insert( (TRACK*) aBoardItem, insertAid ); } break; case TYPE_ZONE: Loading
pcbnew/class_track.cpp +0 −6 Original line number Diff line number Diff line Loading @@ -492,12 +492,6 @@ void SEGVIA::ReturnLayerPair( int* top_layer, int* bottom_layer ) const } /* * Function GetBestInsertPoint * Search the "best" insertion point within the track linked list * the best point is the of the corresponding net code section * return the item found in the linked list (or NULL if no track) */ TRACK* TRACK::GetBestInsertPoint( BOARD* aPcb ) { TRACK* track; Loading
pcbnew/class_zone.cpp +10 −4 Original line number Diff line number Diff line Loading @@ -943,13 +943,19 @@ bool ZONE_CONTAINER::HitTest( EDA_RECT& refArea ) int ZONE_CONTAINER::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const { NETCLASS* myclass = GetNetClass(); int myClearance = m_ZoneClearance; #if 0 // maybe the netclass clearance should not come into play for a zone? #if 0 // Maybe the netclass clearance should not come into play for a zone? // At least the policy decision can be controlled by the zone // itself, i.e. here. On reasons of insufficient documentation, // the user will be less bewildered if we simply respect the // "zone clearance" setting in the zone properties dialog. (At least // until there is a UI boolean for this.) if( myclass ) myClearance = max( myClearance, myclass->GetClearance() ); NETCLASS* myClass = GetNetClass(); if( myClass ) myClearance = std::max( myClearance, myClass->GetClearance() ); #endif if( aItem ) Loading