Fix someminor coverity warning, and one bug found by coverity in drill report...

Fix someminor  coverity warning, and one bug found by coverity in drill report files : buried holes were not properly counted and listed.

eeschema/class_library.cpp

@@ -63,6 +63,8 @@ PART_LIB::PART_LIB( int aType, const wxString& aFileName ) :
     timeStamp = 0;
     isCache = false;
     timeStamp = wxDateTime::Now();
+    versionMajor = 0;       // Will be updated after reading the lib file
+    versionMinor = 0;       // Will be updated after reading the lib file
 
     fileName = aFileName;
 

eeschema/pinedit.cpp

@@ -515,8 +515,6 @@ void LIB_EDIT_FRAME::CreateImagePins( LIB_PIN* aPin, int aUnit, int aConvert, bo
 void LIB_EDIT_FRAME::GlobalSetPins( LIB_PIN* aMasterPin, int aId )
 
 {
-    bool selected = aMasterPin->IsSelected();
-
     LIB_PART*      part = GetCurPart();
 
     if( !part || !aMasterPin )
@@ -527,6 +525,8 @@ void LIB_EDIT_FRAME::GlobalSetPins( LIB_PIN* aMasterPin, int aId )
 
     OnModify( );
 
+    bool selected = aMasterPin->IsSelected();
+
     for( LIB_PIN* pin = part->GetNextPin();  pin;  pin = part->GetNextPin( pin ) )
     {
         if( pin->GetConvert() && pin->GetConvert() != m_convert )

pcbnew/dialogs/dialog_scripting.h

@@ -2,7 +2,7 @@
  * This program source code file is part of KiCad, a free EDA CAD application.
  *
  * Copyright (C) 2012-2014 Miguel Angel Ajo <miguelangel@nbee.es>
- * Copyright (C) 1992-2014 KiCad Developers, see AUTHORS.txt for contributors.
+ * Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -29,9 +29,6 @@
 
 class DIALOG_SCRIPTING: public DIALOG_SCRIPTING_BASE
 {
-private:
-    wxDialog * m_Parent;
-
 public:
     DIALOG_SCRIPTING( wxWindow * parent );
 

pcbnew/exporters/gen_drill_report_files.cpp

@@ -282,18 +282,18 @@ bool EXCELLON_WRITER::GenDrillMapFile( const wxString& aFullFileName,
 
 bool EXCELLON_WRITER::GenDrillReportFile( const wxString& aFullFileName )
 {
-    unsigned    totalHoleCount;
-    char        line[1024];
-    LAYER_NUM   layer1 = B_Cu;
-    LAYER_NUM   layer2 = F_Cu;
-    bool        gen_through_holes   = true;
-    bool        gen_NPTH_holes      = false;
-
     m_file = wxFopen( aFullFileName, wxT( "w" ) );
 
     if( m_file == NULL )
         return false;
 
+    unsigned    totalHoleCount;
+    char        line[1024];
+    LAYER_NUM   layer1 = F_Cu;      // First layer of the stack layer
+    LAYER_NUM   layer2 = B_Cu;      // Last layer of the stack layer
+    bool        gen_through_holes   = true;
+    bool        gen_NPTH_holes      = false;
+
     wxString brdFilename = m_pcb->GetFileName();
     fprintf( m_file, "Drill report for %s\n", TO_UTF8( brdFilename ) );
     fprintf( m_file, "Created on %s\n", TO_UTF8( DateAndTime() ) );
@@ -318,7 +318,7 @@ bool EXCELLON_WRITER::GenDrillReportFile( const wxString& aFullFileName )
         else
         {
             // If this is the first partial hole list: print a title
-            if( layer1 == B_Cu )
+            if( layer1 == F_Cu )
                 fputs( "Drill report for buried and blind vias :\n\n", m_file );
 
             sprintf( line, "Drill report for holes from layer %s to layer %s :\n",
@@ -380,12 +380,12 @@ bool EXCELLON_WRITER::GenDrillReportFile( const wxString& aFullFileName )
             }
 
             if( gen_through_holes )
-            {
+            {   // Prepare the next iteration, which print the not through holes
                 layer2 = layer1 + 1;
             }
             else
             {
-                if( layer2 >= F_Cu )    // no more layer pair to consider
+                if( layer2 >= B_Cu )    // no more layer pair to consider
                 {
                     gen_NPTH_holes = true;
                     continue;
@@ -395,9 +395,7 @@ bool EXCELLON_WRITER::GenDrillReportFile( const wxString& aFullFileName )
                 ++layer2;           // use next layer pair
 
                 if( layer2 == m_pcb->GetCopperLayerCount() - 1 )
-                    layer2 = F_Cu; // the last layer is always the
-
-                // component layer
+                    layer2 = B_Cu; // the last layer is always the bottom layer
             }
 
             gen_through_holes = false;