Pcbnew: fix bug when generating drill files for blind/buried vias. (d6fbfbc0) · Commits · Elphel / kicad-source-mirror

pcbnew/dialogs/dialog_gendrill.cpp

+26 −25

Original line number	Diff line number	Diff line
		@@ -354,15 +354,17 @@ void DIALOG_GENDRILL::SetParams()

		void DIALOG_GENDRILL::GenDrillAndMapFiles(bool aGenDrill, bool aGenMap)
		{
		wxString layer_extend; /* added to the Board FileName to
		wxString layername_extend; /* added to the Board FileName to
		* create FullFileName (= Board
		* FileName + layer pair names) */
		* FileName + layer pair names)
		*/
		wxString msg;
		bool hasBuriedVias = false; /* If true, drill files are created
		* layer pair by layer pair for
		* buried vias */
		int layer1 = B_Cu;
		int layer2 = F_Cu;
		* buried vias
		*/
		int layer1 = F_Cu;
		int layer2 = B_Cu;
		bool gen_through_holes = true;
		bool gen_NPTH_holes = false;

		@@ -392,26 +394,26 @@ void DIALOG_GENDRILL::GenDrillAndMapFiles(bool aGenDrill, bool aGenMap)
		if( excellonWriter.GetHolesCount() > 0 ) // has holes?
		{
		fn = m_parent->GetBoard()->GetFileName();
		layer_extend.Empty();
		layername_extend.Empty();

		if( gen_NPTH_holes )
		{
		layer_extend << wxT( "-NPTH" );
		layername_extend << wxT( "-NPTH" );
		}
		else if( !gen_through_holes )
		{
		if( layer1 == B_Cu )
		layer_extend << wxT( "-back" );
		if( layer1 == F_Cu )
		layername_extend << wxT( "-front" );
		else
		layer_extend << wxT( "-inner" ) << layer1;
		layername_extend << wxT( "-inner" ) << layer1;

		if( layer2 == F_Cu )
		layer_extend << wxT( "-front" );
		if( layer2 == B_Cu )
		layername_extend << wxT( "-back" );
		else
		layer_extend << wxT( "-inner" ) << layer2;
		layername_extend << wxT( "-inner" ) << layer2;
		}

		fn.SetName( fn.GetName() + layer_extend );
		fn.SetName( fn.GetName() + layername_extend );
		wxString defaultPath = m_plotOpts.GetOutputDirectory();

		if( defaultPath.IsEmpty() )
		@@ -469,13 +471,13 @@ void DIALOG_GENDRILL::GenDrillAndMapFiles(bool aGenDrill, bool aGenMap)
		else
		{
		if( gen_through_holes )
		layer2 = layer1 + 1; // prepare generation of first layer pair
		layer2 = layer1 + 1; // done with through-board holes, prepare generation of first layer pair
		else
		{
		if( layer2 >= F_Cu ) // no more layer pair to consider
		if( layer2 >= B_Cu ) // no more layer pair to consider
		{
		layer1 = B_Cu;
		layer2 = F_Cu;
		layer1 = F_Cu;
		layer2 = B_Cu;
		gen_NPTH_holes = true;
		continue;
		}
		@@ -484,8 +486,7 @@ void DIALOG_GENDRILL::GenDrillAndMapFiles(bool aGenDrill, bool aGenMap)
		layer2++; // use next layer pair

		if( layer2 == m_parent->GetBoard()->GetCopperLayerCount() - 1 )
		layer2 = F_Cu; // the last layer is always the
		// Front layer
		layer2 = B_Cu; // the last layer is always the back layer
		}

		gen_through_holes = false;

pcbnew/exporters/gendrill_Excellon_writer.cpp

+10 −7

Original line number	Diff line number	Diff line
		@@ -471,12 +471,13 @@ void EXCELLON_WRITER::BuildHolesList( int aFirstLayer,
		via->LayerPair( &new_hole.m_Hole_Top_Layer, &new_hole.m_Hole_Bottom_Layer );

		// LayerPair return params with m_Hole_Bottom_Layer > m_Hole_Top_Layer
		// (remember top layer = 0 and bottom layer = 31 for through hole vias)
		if( (new_hole.m_Hole_Top_Layer < aFirstLayer) && (aFirstLayer >= 0) )
		continue;
		// Remember: top layer = 0 and bottom layer = 31 for through hole vias
		// the via should be at least from aFirstLayer to aLastLayer
		if( (new_hole.m_Hole_Top_Layer > aFirstLayer) && (aFirstLayer >= 0) )
		continue; // via above the first layer

		if( (new_hole.m_Hole_Bottom_Layer > aLastLayer) && (aLastLayer >= 0) )
		continue;
		if( (new_hole.m_Hole_Bottom_Layer < aLastLayer) && (aLastLayer >= 0) )
		continue; // via below the last layer

		if( aExcludeThroughHoles && (new_hole.m_Hole_Bottom_Layer == B_Cu)
		&& (new_hole.m_Hole_Top_Layer == F_Cu) )
		@@ -494,7 +495,9 @@ void EXCELLON_WRITER::BuildHolesList( int aFirstLayer,
		// Read and analyse pads
		for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
		{
		if( ! aGenerateNPTH_list && pad->GetAttribute() == PAD_HOLE_NOT_PLATED && ! aMergePTHNPTH )
		if( ! aGenerateNPTH_list &&
		pad->GetAttribute() == PAD_HOLE_NOT_PLATED &&
		! aMergePTHNPTH )
		continue;

		if( aGenerateNPTH_list && pad->GetAttribute() != PAD_HOLE_NOT_PLATED )

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