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Commit cfc68722 authored by CHARRAS's avatar CHARRAS
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some translations

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internat/fr/kicad.mo
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internat/fr/kicad.po
View file @ cfc68722
...@@ -2,7 +2,7 @@ msgid "" ...@@ -2,7 +2,7 @@ msgid ""
msgstr "" msgstr ""
"Project-Id-Version: kicad\n" "Project-Id-Version: kicad\n"
"POT-Creation-Date: \n" "POT-Creation-Date: \n"
"PO-Revision-Date: 2007-10-13 19:18+0100\n" "PO-Revision-Date: 2007-10-19 08:14+0100\n"
"Last-Translator: \n" "Last-Translator: \n"
"Language-Team: kicad team <jean-pierre.charras@ujf-grenoble.fr>\n" "Language-Team: kicad team <jean-pierre.charras@ujf-grenoble.fr>\n"
"MIME-Version: 1.0\n" "MIME-Version: 1.0\n"
...@@ -734,8 +734,8 @@ msgstr "Outils" ...@@ -734,8 +734,8 @@ msgstr "Outils"
#: pcbnew/gendrill.cpp:1098 #: pcbnew/gendrill.cpp:1098
#: pcbnew/gendrill.cpp:1674 #: pcbnew/gendrill.cpp:1674
#: pcbnew/class_pad.cpp:995 #: pcbnew/class_pad.cpp:995
#: pcbnew/class_track.cpp:812 #: pcbnew/class_track.cpp:836
#: pcbnew/class_track.cpp:817 #: pcbnew/class_track.cpp:841
msgid "Drill" msgid "Drill"
msgstr "Perage" msgstr "Perage"
...@@ -984,8 +984,8 @@ msgstr "Texte Pcb" ...@@ -984,8 +984,8 @@ msgstr "Texte Pcb"
#: pcbnew/class_text_mod.cpp:347 #: pcbnew/class_text_mod.cpp:347
#: pcbnew/class_text_mod.cpp:351 #: pcbnew/class_text_mod.cpp:351
#: pcbnew/class_pad.cpp:972 #: pcbnew/class_pad.cpp:972
#: pcbnew/class_track.cpp:796
#: pcbnew/dialog_edit_module.cpp:234 #: pcbnew/dialog_edit_module.cpp:234
#: pcbnew/class_track.cpp:820
#: pcbnew/sel_layer.cpp:145 #: pcbnew/sel_layer.cpp:145
#: pcbnew/class_module.cpp:1116 #: pcbnew/class_module.cpp:1116
#: gerbview/affiche.cpp:109 #: gerbview/affiche.cpp:109
...@@ -1035,8 +1035,8 @@ msgstr "Orient" ...@@ -1035,8 +1035,8 @@ msgstr "Orient"
#: pcbnew/classpcb.cpp:202 #: pcbnew/classpcb.cpp:202
#: pcbnew/class_text_mod.cpp:364 #: pcbnew/class_text_mod.cpp:364
#: pcbnew/pcbtexte.cpp:130 #: pcbnew/pcbtexte.cpp:130
#: pcbnew/class_track.cpp:820
#: pcbnew/class_edge_mod.cpp:297 #: pcbnew/class_edge_mod.cpp:297
#: pcbnew/class_track.cpp:844
#: eeschema/affiche.cpp:188 #: eeschema/affiche.cpp:188
#: eeschema/dialog_cmp_graphic_properties.cpp:188 #: eeschema/dialog_cmp_graphic_properties.cpp:188
#: gerbview/affiche.cpp:52 #: gerbview/affiche.cpp:52
...@@ -1558,7 +1558,7 @@ msgstr "Mode d'affichage Haut Contraste" ...@@ -1558,7 +1558,7 @@ msgstr "Mode d'affichage Haut Contraste"
#: pcbnew/pcbframe.cpp:442 #: pcbnew/pcbframe.cpp:442
#: pcbnew/class_board_item.cpp:140 #: pcbnew/class_board_item.cpp:140
#: pcbnew/class_track.cpp:729 #: pcbnew/class_track.cpp:753
msgid "Track" msgid "Track"
msgstr "Piste" msgstr "Piste"
...@@ -1920,10 +1920,6 @@ msgstr "Inclure pistes autorout ...@@ -1920,10 +1920,6 @@ msgstr "Inclure pistes autorout
msgid "Include Locked Tracks" msgid "Include Locked Tracks"
msgstr "Inclure pistes verrouilles" msgstr "Inclure pistes verrouilles"
#: pcbnew/deltrack.cpp:153
msgid "Delete NET ?"
msgstr "Supprimer Net ?"
#: pcbnew/dialog_track_options.cpp:125 #: pcbnew/dialog_track_options.cpp:125
msgid "Via Size" msgid "Via Size"
msgstr "Diametre Via" msgstr "Diametre Via"
...@@ -2004,6 +2000,7 @@ msgid "Filled" ...@@ -2004,6 +2000,7 @@ msgid "Filled"
msgstr "Plein" msgstr "Plein"
#: pcbnew/dialog_display_options.cpp:196 #: pcbnew/dialog_display_options.cpp:196
#: pcbnew/ioascii.cpp:196
msgid "Tracks:" msgid "Tracks:"
msgstr "Pistes:" msgstr "Pistes:"
...@@ -2082,65 +2079,9 @@ msgstr "Afficher autres ...@@ -2082,65 +2079,9 @@ msgstr "Afficher autres
msgid "Show page limits" msgid "Show page limits"
msgstr " Afficher limites de page" msgstr " Afficher limites de page"
#: pcbnew/clean.cpp:163 #: pcbnew/deltrack.cpp:153
msgid "Delete unconnected tracks:" msgid "Delete NET ?"
msgstr "Suppression Pistes non connectes" msgstr "Supprimer Net ?"
#: pcbnew/clean.cpp:181
msgid "ViaDef"
msgstr "ViaDef"
#: pcbnew/clean.cpp:332
msgid "Clean Null Segments"
msgstr "Nettoyage segments nulls"
#: pcbnew/clean.cpp:420
msgid "Merging Segments:"
msgstr "Associe Segment"
#: pcbnew/clean.cpp:422
msgid "Merge"
msgstr "Merge"
#: pcbnew/clean.cpp:422
#: pcbnew/dialog_pad_edit.cpp:186
#: eeschema/dialog_erc.cpp:192
#: eeschema/dialog_erc.cpp:196
#: eeschema/dialog_edit_component_in_schematic.cpp:172
msgid "0"
msgstr "0"
#: pcbnew/clean.cpp:435
msgid "Merge: "
msgstr "Merge: "
#: pcbnew/clean.cpp:647
msgid "DRC Control:"
msgstr "Controle DRC:"
#: pcbnew/clean.cpp:652
msgid "NetCtr"
msgstr "NetCtr"
#: pcbnew/clean.cpp:886
msgid "Centre"
msgstr "Centre"
#: pcbnew/clean.cpp:886
msgid "0 "
msgstr "0"
#: pcbnew/clean.cpp:897
msgid "Pads: "
msgstr "Pastilles: "
#: pcbnew/clean.cpp:900
msgid "Max"
msgstr "Max"
#: pcbnew/clean.cpp:902
msgid "Segm"
msgstr "Segm"
#: pcbnew/plotgerb.cpp:72 #: pcbnew/plotgerb.cpp:72
msgid "unable to create file " msgid "unable to create file "
...@@ -2244,7 +2185,7 @@ msgid "No Net" ...@@ -2244,7 +2185,7 @@ msgid "No Net"
msgstr "No Net" msgstr "No Net"
#: pcbnew/zones.cpp:916 #: pcbnew/zones.cpp:916
#: pcbnew/class_track.cpp:755 #: pcbnew/class_track.cpp:779
msgid "NetName" msgid "NetName"
msgstr "NetName" msgstr "NetName"
...@@ -2432,10 +2373,6 @@ msgstr "Segment en cours d' ...@@ -2432,10 +2373,6 @@ msgstr "Segment en cours d'
msgid "Delete Layer " msgid "Delete Layer "
msgstr "Effacer Couche" msgstr "Effacer Couche"
#: pcbnew/ioascii.cpp:207
msgid "Error: Unexpected end of file !"
msgstr "Erreur: Fin de fichier inattendue !"
#: pcbnew/set_grid.cpp:147 #: pcbnew/set_grid.cpp:147
#: pcbnew/dialog_general_options.cpp:271 #: pcbnew/dialog_general_options.cpp:271
#: gerbview/options.cpp:183 #: gerbview/options.cpp:183
...@@ -2512,7 +2449,7 @@ msgstr "NetName Pad:" ...@@ -2512,7 +2449,7 @@ msgstr "NetName Pad:"
#: pcbnew/dialog_pad_edit.cpp:196 #: pcbnew/dialog_pad_edit.cpp:196
#: pcbnew/classpcb.cpp:186 #: pcbnew/classpcb.cpp:186
#: pcbnew/class_board_item.cpp:108 #: pcbnew/class_board_item.cpp:108
#: pcbnew/class_track.cpp:766 #: pcbnew/class_track.cpp:790
msgid "Circle" msgid "Circle"
msgstr "Cercle" msgstr "Cercle"
...@@ -2525,6 +2462,14 @@ msgstr "Ovale" ...@@ -2525,6 +2462,14 @@ msgstr "Ovale"
msgid "Drill Shape:" msgid "Drill Shape:"
msgstr "Forme du perage:" msgstr "Forme du perage:"
#: pcbnew/dialog_pad_edit.cpp:186
#: pcbnew/clean.cpp:446
#: eeschema/dialog_erc.cpp:192
#: eeschema/dialog_erc.cpp:196
#: eeschema/dialog_edit_component_in_schematic.cpp:172
msgid "0"
msgstr "0"
#: pcbnew/dialog_pad_edit.cpp:187 #: pcbnew/dialog_pad_edit.cpp:187
msgid "90" msgid "90"
msgstr "90" msgstr "90"
...@@ -2562,7 +2507,7 @@ msgid "Pad Shape:" ...@@ -2562,7 +2507,7 @@ msgid "Pad Shape:"
msgstr "Forme Pad:" msgstr "Forme Pad:"
#: pcbnew/dialog_pad_edit.cpp:205 #: pcbnew/dialog_pad_edit.cpp:205
#: pcbnew/class_track.cpp:768 #: pcbnew/class_track.cpp:792
msgid "Standard" msgid "Standard"
msgstr "Standard" msgstr "Standard"
...@@ -2657,6 +2602,14 @@ msgstr "Supprimer Module" ...@@ -2657,6 +2602,14 @@ msgstr "Supprimer Module"
msgid "Value " msgid "Value "
msgstr "Valeur " msgstr "Valeur "
#: pcbnew/ioascii.cpp:200
msgid "Zones:"
msgstr "Zones:"
#: pcbnew/ioascii.cpp:207
msgid "Error: Unexpected end of file !"
msgstr "Erreur: Fin de fichier inattendue !"
#: pcbnew/pcbcfg.cpp:68 #: pcbnew/pcbcfg.cpp:68
#: eeschema/eeconfig.cpp:58 #: eeschema/eeconfig.cpp:58
#: cvpcb/menucfg.cpp:170 #: cvpcb/menucfg.cpp:170
...@@ -2709,10 +2662,62 @@ msgstr "Librairie: " ...@@ -2709,10 +2662,62 @@ msgstr "Librairie: "
msgid "Modules (%d items)" msgid "Modules (%d items)"
msgstr "Modules (%d lments)" msgstr "Modules (%d lments)"
#: pcbnew/clean.cpp:169
msgid "Delete unconnected tracks:"
msgstr "Suppression Pistes non connectes"
#: pcbnew/clean.cpp:188
msgid "ViaDef"
msgstr "ViaDef"
#: pcbnew/clean.cpp:348
msgid "Clean Null Segments"
msgstr "Nettoyage segments nulls"
#: pcbnew/clean.cpp:444
msgid "Merging Segments:"
msgstr "Associe Segment"
#: pcbnew/clean.cpp:446
msgid "Merge"
msgstr "Merge"
#: pcbnew/clean.cpp:460
msgid "Merge: "
msgstr "Merge: "
#: pcbnew/clean.cpp:680
msgid "DRC Control:"
msgstr "Controle DRC:"
#: pcbnew/clean.cpp:685
msgid "NetCtr"
msgstr "NetCtr"
#: pcbnew/clean.cpp:963
msgid "Centre"
msgstr "Centre"
#: pcbnew/clean.cpp:963
msgid "0 "
msgstr "0"
#: pcbnew/clean.cpp:976
msgid "Pads: "
msgstr "Pastilles: "
#: pcbnew/clean.cpp:980
msgid "Max"
msgstr "Max"
#: pcbnew/clean.cpp:983
msgid "Segm"
msgstr "Segm"
#: pcbnew/classpcb.cpp:181 #: pcbnew/classpcb.cpp:181
#: pcbnew/classpcb.cpp:313 #: pcbnew/classpcb.cpp:313
#: pcbnew/class_text_mod.cpp:337 #: pcbnew/class_text_mod.cpp:337
#: pcbnew/class_track.cpp:740 #: pcbnew/class_track.cpp:764
#: gerbview/affiche.cpp:93 #: gerbview/affiche.cpp:93
msgid "Type" msgid "Type"
msgstr "Type" msgstr "Type"
...@@ -2726,7 +2731,7 @@ msgid " Arc " ...@@ -2726,7 +2731,7 @@ msgid " Arc "
msgstr " Arc " msgstr " Arc "
#: pcbnew/classpcb.cpp:195 #: pcbnew/classpcb.cpp:195
#: pcbnew/class_track.cpp:764 #: pcbnew/class_track.cpp:788
msgid "Segment" msgid "Segment"
msgstr "Segment" msgstr "Segment"
...@@ -3586,7 +3591,7 @@ msgid "Length:" ...@@ -3586,7 +3591,7 @@ msgid "Length:"
msgstr "Long.:" msgstr "Long.:"
#: pcbnew/class_board_item.cpp:153 #: pcbnew/class_board_item.cpp:153
#: pcbnew/class_track.cpp:733 #: pcbnew/class_track.cpp:757
msgid "Zone" msgid "Zone"
msgstr "Zone" msgstr "Zone"
...@@ -4013,19 +4018,6 @@ msgstr "Deselection" ...@@ -4013,19 +4018,6 @@ msgstr "Deselection"
msgid "Deselect this layer to restore its No Change state" msgid "Deselect this layer to restore its No Change state"
msgstr "Deselectionner cette couche pour restorer l'option Pas de Changement" msgstr "Deselectionner cette couche pour restorer l'option Pas de Changement"
#: pcbnew/class_track.cpp:760
msgid "NetCode"
msgstr "NetCode"
#: pcbnew/class_track.cpp:780
#: pcbnew/class_module.cpp:1135
msgid "Stat"
msgstr "Stat"
#: pcbnew/class_track.cpp:804
msgid "Diam"
msgstr "Diam"
#: pcbnew/dialog_edit_module.cpp:39 #: pcbnew/dialog_edit_module.cpp:39
msgid "Module properties" msgid "Module properties"
msgstr "Proprits du Module" msgstr "Proprits du Module"
...@@ -4200,6 +4192,19 @@ msgstr "Couche Mod." ...@@ -4200,6 +4192,19 @@ msgstr "Couche Mod."
msgid "Seg Layer" msgid "Seg Layer"
msgstr "Couche Seg." msgstr "Couche Seg."
#: pcbnew/class_track.cpp:784
msgid "NetCode"
msgstr "NetCode"
#: pcbnew/class_track.cpp:804
#: pcbnew/class_module.cpp:1135
msgid "Stat"
msgstr "Stat"
#: pcbnew/class_track.cpp:828
msgid "Diam"
msgstr "Diam"
#: pcbnew/moduleframe.cpp:177 #: pcbnew/moduleframe.cpp:177
msgid "Module Editor: module modified!, Continue ?" msgid "Module Editor: module modified!, Continue ?"
msgstr "Editeur de Module: module modifi! Continuer ?" msgstr "Editeur de Module: module modifi! Continuer ?"
......
pcbnew/class_board_item.cpp
View file @ cfc68722
...@@ -170,9 +170,9 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const ...@@ -170,9 +170,9 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
text << _( "Via" ) << wxT( " " ) << via->ShowWidth(); text << _( "Via" ) << wxT( " " ) << via->ShowWidth();
int shape = via->Shape(); int shape = via->Shape();
if( shape == VIA_ENTERREE ) if( shape == BURIED_VIA )
text << wxT(" ") << _( "Blind" ); text << wxT(" ") << _( "Blind" );
else if( shape == VIA_BORGNE ) else if( shape == BLIND_VIA )
text << wxT(" ") << _("Buried"); text << wxT(" ") << _("Buried");
// else say nothing about normal vias // else say nothing about normal vias
...@@ -182,7 +182,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const ...@@ -182,7 +182,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const
text << wxT( " [" ) << net->m_Netname << wxT( "]" ); text << wxT( " [" ) << net->m_Netname << wxT( "]" );
} }
if( shape != VIA_NORMALE ) if( shape != THROUGH_VIA )
{ {
// say which layers, only two for now // say which layers, only two for now
int topLayer; int topLayer;
......
pcbnew/class_track.cpp
View file @ cfc68722
This diff is collapsed.
pcbnew/class_track.h
View file @ cfc68722
/*******************************************************************/ /*******************************************************************/
/* class_track.h: definition des structures de donnees type track */ /* class_track.h: definitions relatives to tracks, vias and zones */
/*******************************************************************/ /*******************************************************************/
#ifndef CLASS_TRACK_H #ifndef CLASS_TRACK_H
...@@ -15,10 +15,6 @@ ...@@ -15,10 +15,6 @@
#define NOT_DEFINED_VIA 0 /* reserved (unused) */ #define NOT_DEFINED_VIA 0 /* reserved (unused) */
#define SQUARE_VIA_SHAPE 0x80000000 /* Flag pour forme carree */ #define SQUARE_VIA_SHAPE 0x80000000 /* Flag pour forme carree */
#define VIA_NORMALE THROUGH_VIA
#define VIA_ENTERREE BURIED_VIA
#define VIA_BORGNE BLIND_VIA
/***/ /***/
class TRACK : public BOARD_ITEM class TRACK : public BOARD_ITEM
...@@ -78,18 +74,20 @@ public: ...@@ -78,18 +74,20 @@ public:
*/ */
void Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint ); void Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint );
/* Recherche du meilleur point d'insertion */ /*Search the "best" insertion point within the track linked list
* the best point is the of the corresponding net code section
* @return the item found in the linked list (or NULL if no track)
*/
TRACK* GetBestInsertPoint( BOARD* Pcb ); TRACK* GetBestInsertPoint( BOARD* Pcb );
/* Copie d'un Element d'une chaine de n elements /* Search (within the track linked list) the first segment matching the netcode
* TRACK* CopyList( int NbSegm = 1 ) const; * ( the linked list is always sorted by net codes )
*/ */
/* Recherche du debut du net
* ( les elements sont classes par net_code croissant ) */
TRACK* GetStartNetCode( int NetCode ); TRACK* GetStartNetCode( int NetCode );
/* Recherche de la fin du net */ /* Search (within the track linked list) the last segment matching the netcode
* ( the linked list is always sorted by net codes )
*/
TRACK* GetEndNetCode( int NetCode ); TRACK* GetEndNetCode( int NetCode );
/** /**
......
pcbnew/classpcb.cpp
View file @ cfc68722
...@@ -433,7 +433,7 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() ...@@ -433,7 +433,7 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_CopperLayerCount = 2; // Default design is a double sided board m_CopperLayerCount = 2; // Default design is a double sided board
m_ViaDrill = 250; // via drill (for the entire board) m_ViaDrill = 250; // via drill (for the entire board)
m_CurrentViaSize = 450; // Current via size m_CurrentViaSize = 450; // Current via size
m_CurrentViaType = VIA_NORMALE; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/ m_CurrentViaType = THROUGH_VIA; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
m_CurrentTrackWidth = 170; // current track width m_CurrentTrackWidth = 170; // current track width
for( ii = 0; ii < HIST0RY_NUMBER; ii++ ) for( ii = 0; ii < HIST0RY_NUMBER; ii++ )
{ {
...@@ -454,9 +454,9 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() ...@@ -454,9 +454,9 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings()
m_LayerColor[ii] = default_layer_color[ii]; m_LayerColor[ii] = default_layer_color[ii];
// Layer colors (tracks and graphic items) // Layer colors (tracks and graphic items)
m_ViaColor[VIA_BORGNE] = CYAN; m_ViaColor[BLIND_VIA] = CYAN;
m_ViaColor[VIA_ENTERREE] = BROWN; m_ViaColor[BURIED_VIA] = BROWN;
m_ViaColor[VIA_NORMALE] = WHITE; m_ViaColor[THROUGH_VIA] = WHITE;
m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer
m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer
m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed) m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed)
......
pcbnew/classtrc.cpp.notused deleted 100644 → 0
View file @ 387a8763
This diff is collapsed.
pcbnew/clean.cpp
View file @ cfc68722
...@@ -81,7 +81,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) ...@@ -81,7 +81,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
TRACK* next_track; TRACK* next_track;
for( track = frame->m_Pcb->m_Track; track != NULL; track = track->Next() ) for( track = frame->m_Pcb->m_Track; track != NULL; track = track->Next() )
{ {
if( track->m_Shape != VIA_NORMALE ) if( track->m_Shape != THROUGH_VIA )
continue; continue;
/* Search and delete others vias at same location */ /* Search and delete others vias at same location */
...@@ -89,7 +89,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) ...@@ -89,7 +89,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
for( ; alt_track != NULL; alt_track = next_track ) for( ; alt_track != NULL; alt_track = next_track )
{ {
next_track = alt_track->Next(); next_track = alt_track->Next();
if( alt_track->m_Shape != VIA_NORMALE ) if( alt_track->m_Shape != THROUGH_VIA )
continue; continue;
if( alt_track->m_Start != track->m_Start ) if( alt_track->m_Start != track->m_Start )
...@@ -105,7 +105,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) ...@@ -105,7 +105,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC )
for( track = frame->m_Pcb->m_Track; track != NULL; track = next_track ) for( track = frame->m_Pcb->m_Track; track != NULL; track = next_track )
{ {
next_track = track->Next(); next_track = track->Next();
if( track->m_Shape != VIA_NORMALE ) if( track->m_Shape != THROUGH_VIA )
continue; continue;
D_PAD* pad = Fast_Locate_Pad_Connecte( frame->m_Pcb, track->m_Start, ALL_CU_LAYERS ); D_PAD* pad = Fast_Locate_Pad_Connecte( frame->m_Pcb, track->m_Start, ALL_CU_LAYERS );
......
pcbnew/dialog_track_options.cpp
View file @ cfc68722
...@@ -251,11 +251,11 @@ void WinEDA_PcbTracksDialog::AcceptPcbOptions(wxCommandEvent& event) ...@@ -251,11 +251,11 @@ void WinEDA_PcbTracksDialog::AcceptPcbOptions(wxCommandEvent& event)
/*******************************************************************/ /*******************************************************************/
{ {
g_DesignSettings.m_CurrentViaType = m_OptViaType->GetSelection() + 1; g_DesignSettings.m_CurrentViaType = m_OptViaType->GetSelection() + 1;
if ( g_DesignSettings.m_CurrentViaType != VIA_NORMALE ) if ( g_DesignSettings.m_CurrentViaType != THROUGH_VIA )
{ {
if( ! IsOK(this, if( ! IsOK(this,
_("You have selected VIA Blind or VIA Buried\nWARNING: this feature is EXPERIMENTAL!!! Accept ?") ) ) _("You have selected VIA Blind or VIA Buried\nWARNING: this feature is EXPERIMENTAL!!! Accept ?") ) )
g_DesignSettings.m_CurrentViaType = VIA_NORMALE; g_DesignSettings.m_CurrentViaType = THROUGH_VIA;
} }
g_DesignSettings.m_CurrentViaSize = g_DesignSettings.m_CurrentViaSize =
......
pcbnew/editrack-part2.cpp
View file @ cfc68722
...@@ -231,12 +231,12 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) ...@@ -231,12 +231,12 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC )
GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM; GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM;
/* Adjust the via layer pair */ /* Adjust the via layer pair */
if( Via->Shape() == VIA_ENTERREE ) if( Via->Shape() == BURIED_VIA )
{ {
Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
} }
else if( Via->Shape() == VIA_BORGNE ) //blind via else if( Via->Shape() == BLIND_VIA ) //blind via
{ {
// A revoir! ( la via devrait deboucher sur 1 cote ) // A revoir! ( la via devrait deboucher sur 1 cote )
Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
......
pcbnew/router.cpp
View file @ cfc68722
...@@ -604,9 +604,9 @@ void WinEDA_PcbFrame::ReadAutoroutedTracks( wxDC* DC ) ...@@ -604,9 +604,9 @@ void WinEDA_PcbFrame::ReadAutoroutedTracks( wxDC* DC )
NewVia->m_Width = via_size; NewVia->m_Width = via_size;
NewVia->SetLayer( via_layer1 + (via_layer2 << 4) ); NewVia->SetLayer( via_layer1 + (via_layer2 << 4) );
if( NewVia->GetLayer() == 0x0F || NewVia->GetLayer() == 0xF0 ) if( NewVia->GetLayer() == 0x0F || NewVia->GetLayer() == 0xF0 )
NewVia->m_Shape = VIA_NORMALE; NewVia->m_Shape = THROUGH_VIA;
else else
NewVia->m_Shape = VIA_ENTERREE; NewVia->m_Shape = BURIED_VIA;
NewVia->Insert( m_Pcb, NULL ); NewVia->Insert( m_Pcb, NULL );
NbTrack++; NbTrack++;
......
pcbnew/swap_layers.cpp
View file @ cfc68722
...@@ -218,7 +218,7 @@ void WinEDA_PcbFrame::Swap_Layers( wxCommandEvent& event ) ...@@ -218,7 +218,7 @@ void WinEDA_PcbFrame::Swap_Layers( wxCommandEvent& event )
if( pt_segm->Type() == TYPEVIA ) if( pt_segm->Type() == TYPEVIA )
{ {
SEGVIA* Via = (SEGVIA*) pt_segm; SEGVIA* Via = (SEGVIA*) pt_segm;
if( Via->Shape() == VIA_NORMALE ) if( Via->Shape() == THROUGH_VIA )
continue; continue;
int top_layer, bottom_layer; int top_layer, bottom_layer;
Via->ReturnLayerPair( &top_layer, &bottom_layer ); Via->ReturnLayerPair( &top_layer, &bottom_layer );
......
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