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Elphel
kicad-source-mirror
Commits
b39408b1
Commit
b39408b1
authored
Feb 04, 2014
by
Miguel Angel Ajo
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Adding a first BOARD class tester, very basic
parent
ec9c949c
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2
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+36
-0
test_001_pcb_load.py
qa/testcases/test_001_pcb_load.py
+1
-0
test_002_board_class.py
qa/testcases/test_002_board_class.py
+35
-0
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qa/testcases/test_001_pcb_load.py
View file @
b39408b1
import
code
import
unittest
import
pcbnew
import
pdb
class
TestPCBLoad
(
unittest
.
TestCase
):
...
...
qa/testcases/test_002_board_class.py
0 → 100644
View file @
b39408b1
import
code
import
unittest
import
pcbnew
import
pdb
from
pcbnew
import
ToMM
class
TestBoardClass
(
unittest
.
TestCase
):
def
setUp
(
self
):
self
.
pcb
=
pcbnew
.
LoadBoard
(
"data/complex_hierarchy.kicad_pcb"
)
def
test_pcb_find_module
(
self
):
module
=
self
.
pcb
.
FindModule
(
'P1'
)
self
.
assertEqual
(
module
.
GetReference
(),
'P1'
)
def
test_pcb_bounding_box
(
self
):
bounding_box
=
self
.
pcb
.
ComputeBoundingBox
()
height
=
ToMM
(
bounding_box
.
GetHeight
()
)
width
=
ToMM
(
bounding_box
.
GetWidth
()
)
# probably it's a cleaner test to generate a board with
# a couple of things, that we can know the exact size,
# and then compute the bounding box,
self
.
assertAlmostEqual
(
height
,
89.52
,
2
)
self
.
assertAlmostEqual
(
width
,
108.44
,
2
)
#def test_interactive(self):
# code.interact(local=locals())
if
__name__
==
'__main__'
:
unittest
.
main
()
\ No newline at end of file
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