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kicad-source-mirror
Commit aaf6cce6 authored by Brian Sidebotham's avatar Brian Sidebotham Committed by Dick Hollenbeck
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switch a template's board format to kicad_pcb format

parent 08f87038
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template/raspberrypi-gpio/meta/brd.png 100644 → 100755
View replaced file @ 08f87038 View file @ aaf6cce6
template/raspberrypi-gpio/meta/brd.png

13.4 KB | W: | H:

template/raspberrypi-gpio/meta/brd.png

56.2 KB | W: | H:

template/raspberrypi-gpio/meta/brd.png
template/raspberrypi-gpio/meta/brd.png
template/raspberrypi-gpio/meta/brd.png
template/raspberrypi-gpio/meta/brd.png
  • 2-up
  • Swipe
  • Onion skin
template/raspberrypi-gpio/meta/icon.png 100644 → 100755
View file @ aaf6cce6
File mode changed from 100644 to 100755
template/raspberrypi-gpio/meta/info.html 100644 → 100755
View file @ aaf6cce6
...@@ -5,19 +5,21 @@ ...@@ -5,19 +5,21 @@
<body> <body>
<h1>Raspberry Pi</h1> <h1>Raspberry Pi</h1>
<h2>Expansion Board</h2> <h2>Expansion Board</h2>
This project template is the basis of an expansion board for the
<p>This project template is the basis of an expansion board for the
<a href="http://www.raspberrypi.org/" target="blank">Raspberry Pi $25 ARM <a href="http://www.raspberrypi.org/" target="blank">Raspberry Pi $25 ARM
board.</a> board.</a></p>
<br><br>
This base project includes a PCB edge defined as the same size as the <p>This base project includes a PCB edge defined as the same size as the
Raspberry-Pi PCB with the connectors placed correctly to align the two boards. Raspberry-Pi PCB with the connectors placed correctly to align the two boards.
All IO present on the Raspberry-Pi board is connected to the project through the All IO present on the Raspberry-Pi board is connected to the project through the
0.1" expansion headers. 0.1" expansion headers.</p>
<br><br>
The board outline looks like the following: <p>The board outline looks like the following:</p>
<P><IMG SRC="brd.png" NAME="brd" ALIGN=LEFT WIDTH=680 HEIGHT=378 BORDER=0><BR><BR>(c)2012
<br><br> <p><img src="brd.png"></p>
(c)2012 Brian Sidebotham<br>
(c)2012 Kicad Developers<br> <p>(c)2012 Brian Sidebotham<br>
(c)2012 Kicad Developers<br></p>
</body> </body>
</html> </html>
template/raspberrypi-gpio/raspberrypi-gpio-cache.lib 100644 → 100755
View file @ aaf6cce6
EESchema-LIBRARY Version 2.3 Date: 03/08/2012 23:04:32 EESchema-LIBRARY Version 2.3 Date: 15/11/2012 21:22:43
#encoding utf-8 #encoding utf-8
# #
# +3.3V # +3.3V
......
template/raspberrypi-gpio/raspberrypi-gpio.brd deleted 100644 → 0
View file @ 08f87038
PCBNEW-BOARD Version 1 date 03/08/2012 23:04:25
# Created by Pcbnew(2012-08-03 BZR 3666)-testing
$GENERAL
encoding utf-8
Units deci-mils
LayerCount 2
EnabledLayers 1FFF8001
VisibleLayers 1FFFFFFF
Links 0
NoConn 0
Di 64424 41924 100576 63576
Ndraw 4
Ntrack 0
Nzone 0
BoardThickness 620
Nmodule 1
Nnets 4
$EndGENERAL
$SHEETDESCR
Sheet A3 16535 11693
Title ""
Date "3 aug 2012"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndSHEETDESCR
$SETUP
Layers 2
Layer[0] Back signal
Layer[15] Front signal
TrackWidth 100
TrackClearence 100
ZoneClearence 200
Zone_45_Only 0
TrackMinWidth 100
DrawSegmWidth 150
EdgeSegmWidth 150
ViaSize 350
ViaDrill 250
ViaMinSize 350
ViaMinDrill 200
MicroViaSize 200
MicroViaDrill 50
MicroViasAllowed 0
MicroViaMinSize 200
MicroViaMinDrill 50
TextPcbWidth 120
TextPcbSize 600 800
EdgeModWidth 150
TextModSize 600 600
TextModWidth 120
PadSize 600 600
PadDrill 320
Pad2MaskClearance 100
AuxiliaryAxisOrg 0 0
VisibleElements FFFFFFBF
PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
$EndSETUP
$EQUIPOT
Na 0 ""
St ~
$EndEQUIPOT
$EQUIPOT
Na 1 "+3.3V"
St ~
$EndEQUIPOT
$EQUIPOT
Na 2 "+5V"
St ~
$EndEQUIPOT
$EQUIPOT
Na 3 "GND"
St ~
$EndEQUIPOT
$NCLASS
Name "Default"
Desc "This is the default net class."
Clearance 100
TrackWidth 100
ViaDia 350
ViaDrill 250
uViaDia 200
uViaDrill 50
AddNet ""
AddNet "+3.3V"
AddNet "+5V"
AddNet "GND"
$EndNCLASS
$MODULE pin_array_13x2
Po 71500 43500 0 15 501C4AA3 501C493E ~~
Li pin_array_13x2
Cd Double rangee de contacts 2 x 12 pins
Kw CONN
Sc 501C493E
AR /501C45CC
Op 0 0 0
T0 -6000 1500 400 400 0 80 N V 21 N "P1"
T1 4500 1500 400 400 0 80 N V 21 N "CONN_13X2"
DS -6500 1000 6500 1000 80 21
DS 6500 -1000 -6500 -1000 80 21
DS -6500 -1000 -6500 1000 80 21
DS 6500 1000 6500 -1000 80 21
$PAD
Sh "1" R 600 600 0 0 0
Dr 320 0 0
At STD N 00E0FFFF
Ne 1 "+3.3V"
Po -6000 500
$EndPAD
$PAD
Sh "2" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 2 "+5V"
Po -6000 -500
$EndPAD
$PAD
Sh "3" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5000 500
$EndPAD
$PAD
Sh "4" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -5000 -500
$EndPAD
$PAD
Sh "5" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -4000 500
$EndPAD
$PAD
Sh "6" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 3 "GND"
Po -4000 -500
$EndPAD
$PAD
Sh "7" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3000 500
$EndPAD
$PAD
Sh "8" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -3000 -500
$EndPAD
$PAD
Sh "9" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2000 500
$EndPAD
$PAD
Sh "10" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -2000 -500
$EndPAD
$PAD
Sh "11" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1000 500
$EndPAD
$PAD
Sh "12" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po -1000 -500
$EndPAD
$PAD
Sh "13" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 0 500
$EndPAD
$PAD
Sh "14" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 0 -500
$EndPAD
$PAD
Sh "15" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1000 500
$EndPAD
$PAD
Sh "16" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 1000 -500
$EndPAD
$PAD
Sh "17" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2000 500
$EndPAD
$PAD
Sh "18" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 2000 -500
$EndPAD
$PAD
Sh "19" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3000 500
$EndPAD
$PAD
Sh "20" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 3000 -500
$EndPAD
$PAD
Sh "21" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 4000 500
$EndPAD
$PAD
Sh "22" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 4000 -500
$EndPAD
$PAD
Sh "23" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 5000 500
$EndPAD
$PAD
Sh "24" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 5000 -500
$EndPAD
$PAD
Sh "25" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 6000 500
$EndPAD
$PAD
Sh "26" C 600 600 0 0 0
Dr 400 0 0
At STD N 00E0FFFF
Ne 0 ""
Po 6000 -500
$EndPAD
$SHAPE3D
Na "pin_array/pins_array_13x2.wrl"
Sc 1 1 1
Of 0 0 0
Ro 0 0 0
$EndSHAPE3D
$EndMODULE pin_array_13x2
$DRAWSEGMENT
Po 0 100500 63500 64500 63500 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 64500 42000 64500 63500 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 100500 42000 100500 63500 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$DRAWSEGMENT
Po 0 64500 42000 100500 42000 150
De 28 0 900 0 0
$EndDRAWSEGMENT
$TRACK
$EndTRACK
$ZONE
$EndZONE
$EndBOARD
template/raspberrypi-gpio/raspberrypi-gpio.cmp 100644 → 100755
View file @ aaf6cce6
Cmp-Mod V01 Created by CvPcb (2012-08-03 BZR 3666)-testing date = 03/08/2012 22:59:51 Cmp-Mod V01 Created by CvPcb (2012-11-15 BZR 3804)-testing date = 15/11/2012 21:23:25
BeginCmp BeginCmp
TimeStamp = /501C45CC; TimeStamp = /50A55ABA;
Reference = P1; Reference = P1;
ValeurCmp = CONN_13X2; ValeurCmp = CONN_13X2;
IdModule = pin_array_13x2; IdModule = pin_array_13x2;
......
template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb 0 → 100755
View file @ aaf6cce6
(kicad_pcb (version 3) (host pcbnew "(2012-11-30 BZR 3829)-testing")
(general
(links 0)
(no_connects 0)
(area 127.606667 112.000001 242.964763 190.8)
(thickness 1.6)
(drawings 41)
(tracks 0)
(zones 0)
(modules 1)
(nets 4)
)
(page A3)
(title_block
(date "15 nov 2012")
)
(layers
(15 F.Cu signal)
(0 B.Cu signal)
(16 B.Adhes user)
(17 F.Adhes user)
(18 B.Paste user)
(19 F.Paste user)
(20 B.SilkS user)
(21 F.SilkS user)
(22 B.Mask user)
(23 F.Mask user)
(24 Dwgs.User user)
(25 Cmts.User user)
(26 Eco1.User user)
(27 Eco2.User user)
(28 Edge.Cuts user)
)
(setup
(last_trace_width 0.2)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.1524)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.9)
(via_drill 0.6)
(via_min_size 0.8)
(via_min_drill 0.5)
(uvia_size 0.5)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.5)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1 1)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1 1)
(pad_drill 0.6)
(pad_to_mask_clearance 0)
(aux_axis_origin 143.5 181)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 3178497)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 152400)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotothertext true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 +3.3V)
(net 2 +5V)
(net 3 GND)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.2)
(via_dia 0.9)
(via_drill 0.6)
(uvia_dia 0.5)
(uvia_drill 0.1)
(add_net "")
(add_net +3.3V)
(add_net +5V)
(add_net GND)
)
(net_class Power ""
(clearance 0.2)
(trace_width 0.5)
(via_dia 1)
(via_drill 0.7)
(uvia_dia 0.5)
(uvia_drill 0.1)
)
(module pin_array_13x2 (layer F.Cu) (tedit 50A55E7A) (tstamp 50A55DA3)
(at 161 129)
(descr "Double rangee de contacts 2 x 12 pins")
(tags CONN)
(path /50A55ABA)
(fp_text reference P1 (at -15.5 4) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.2032)))
)
(fp_text value CONN_13X2 (at 12 4) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.2032)))
)
(fp_line (start -16.51 2.54) (end 16.51 2.54) (layer F.SilkS) (width 0.2032))
(fp_line (start 16.51 -2.54) (end -16.51 -2.54) (layer F.SilkS) (width 0.2032))
(fp_line (start -16.51 -2.54) (end -16.51 2.54) (layer F.SilkS) (width 0.2032))
(fp_line (start 16.51 2.54) (end 16.51 -2.54) (layer F.SilkS) (width 0.2032))
(pad 1 thru_hole rect (at -15.24 1.27) (size 1.524 1.524) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 1 +3.3V)
)
(pad 2 thru_hole circle (at -15.24 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
(net 2 +5V)
)
(pad 3 thru_hole circle (at -12.7 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 4 thru_hole circle (at -12.7 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 5 thru_hole circle (at -10.16 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 6 thru_hole circle (at -10.16 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
(net 3 GND)
)
(pad 7 thru_hole circle (at -7.62 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 8 thru_hole circle (at -7.62 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 9 thru_hole circle (at -5.08 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 10 thru_hole circle (at -5.08 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 11 thru_hole circle (at -2.54 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 12 thru_hole circle (at -2.54 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 13 thru_hole circle (at 0 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 14 thru_hole circle (at 0 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 15 thru_hole circle (at 2.54 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 16 thru_hole circle (at 2.54 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 17 thru_hole circle (at 5.08 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 18 thru_hole circle (at 5.08 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 19 thru_hole circle (at 7.62 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 20 thru_hole circle (at 7.62 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 21 thru_hole circle (at 10.16 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 22 thru_hole circle (at 10.16 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 23 thru_hole circle (at 12.7 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 24 thru_hole circle (at 12.7 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 25 thru_hole circle (at 15.24 1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(pad 26 thru_hole circle (at 15.24 -1.27) (size 1.524 1.524) (drill 1.016)
(layers *.Cu *.Mask F.SilkS)
)
(model pin_array/pins_array_13x2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_text "RASPBERRY-PI ADDON BOARD\nVIEW FROM TOP\nNOTE: P1 SHOULD BE FITTED ON THE REVERSE OF THE BOARD" (at 144 183.5) (layer Dwgs.User)
(effects (font (size 2 1.7) (thickness 0.12)) (justify left))
)
(dimension 56 (width 0.12) (layer Dwgs.User)
(gr_text "56.000 mm" (at 132 153 90) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(feature1 (pts (xy 143.5 125) (xy 131 125)))
(feature2 (pts (xy 143.5 181) (xy 131 181)))
(crossbar (pts (xy 133 181) (xy 133 125)))
(arrow1a (pts (xy 133 125) (xy 133.58642 126.126503)))
(arrow1b (pts (xy 133 125) (xy 132.41358 126.126503)))
(arrow2a (pts (xy 133 181) (xy 133.58642 179.873497)))
(arrow2b (pts (xy 133 181) (xy 132.41358 179.873497)))
)
(dimension 85 (width 0.12) (layer Dwgs.User)
(gr_text "85.000 mm" (at 186 113.000001) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(feature1 (pts (xy 228.5 125) (xy 228.5 112.000001)))
(feature2 (pts (xy 143.5 125) (xy 143.5 112.000001)))
(crossbar (pts (xy 143.5 114.000001) (xy 228.5 114.000001)))
(arrow1a (pts (xy 228.5 114.000001) (xy 227.373497 114.586421)))
(arrow1b (pts (xy 228.5 114.000001) (xy 227.373497 113.413581)))
(arrow2a (pts (xy 143.5 114.000001) (xy 144.626503 114.586421)))
(arrow2b (pts (xy 143.5 114.000001) (xy 144.626503 113.413581)))
)
(gr_text "RCA\nREMOVE WITH\nSTD HEADERS\n!NO TH ABOVE!" (at 188.5 118) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(gr_text "1/8\" JACK\nOK WITH STD\nHEADERS\n!NO TH ABOVE!" (at 207.5 118) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(gr_line (start 228.5 142) (end 228.5 125) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 228.5 181) (end 228.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_text "DOUBLE USB\nCUTOUT FOR ALL\nBOARDS" (at 236.5 149) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(gr_text "RJ45\nCUTOUT FOR STD\nHEADERS\n!NO TH ABOVE!" (at 236.5 170) (layer Dwgs.User)
(effects (font (size 1 1) (thickness 0.12)))
)
(gr_line (start 207.5 181) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 207.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 207.5 162) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 207.5 181) (end 207.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 228.5 181) (end 207.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 228.5 162) (end 228.5 181) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 217.5 157) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 217.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 228.5 142) (end 228.5 157) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 182.5 125) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 182.5 139) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 194.5 139) (end 194.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 182.5 139) (end 194.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 182.5 138) (end 182.5 139) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 214.5 125) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 200.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 200.5 138) (end 200.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 214.5 138) (end 200.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 214.5 125) (end 214.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 200.5 125) (end 214.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 194.5 125) (end 182.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 194.5 138) (end 194.5 125) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 182.5 125) (end 182.5 138) (angle 90) (layer Dwgs.User) (width 0.2))
(gr_line (start 228.5 125) (end 143.5 125) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 143.5 181) (end 228.5 181) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 143.5 125) (end 143.5 181) (angle 90) (layer Edge.Cuts) (width 0.15))
)
template/raspberrypi-gpio/raspberrypi-gpio.net 100644 → 100755
View file @ aaf6cce6
# EESchema Netlist Version 1.1 created 03/08/2012 22:54:12 # EESchema Netlist Version 1.1 created 15/11/2012 21:22:35
( (
( /501C45CC $noname P1 CONN_13X2 {Lib=CONN_13X2} ( /50A55ABA $noname P1 CONN_13X2 {Lib=CONN_13X2}
( 1 +3.3V ) ( 1 +3.3V )
( 2 +5V ) ( 2 +5V )
( 3 ? ) ( 3 ? )
......
template/raspberrypi-gpio/raspberrypi-gpio.pro 100644 → 100755
View file @ aaf6cce6
update=03/08/2012 22:36:35 update=15/11/2012 21:11:59
version=1 version=1
last_client=kicad last_client=kicad
[cvpcb] [cvpcb]
......
template/raspberrypi-gpio/raspberrypi-gpio.sch 100644 → 100755
View file @ aaf6cce6
EESchema Schematic File Version 2 date 03/08/2012 23:04:32 EESchema Schematic File Version 2 date 15/11/2012 21:22:43
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
...@@ -29,13 +29,14 @@ LIBS:opto ...@@ -29,13 +29,14 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
EELAYER 43 0 LIBS:rpi-cache
EELAYER 27 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 1 Sheet 1 1
Title "" Title ""
Date "3 aug 2012" Date "15 nov 2012"
Rev "" Rev ""
Comp "" Comp ""
Comment1 "" Comment1 ""
...@@ -45,124 +46,124 @@ Comment4 "" ...@@ -45,124 +46,124 @@ Comment4 ""
$EndDescr $EndDescr
$Comp $Comp
L CONN_13X2 P1 L CONN_13X2 P1
U 1 1 501C45CC U 1 1 50A55ABA
P 9600 1500 P 2400 1800
F 0 "P1" H 9600 2200 60 0000 C CNN F 0 "P1" H 2400 2500 60 0000 C CNN
F 1 "CONN_13X2" V 9600 1500 50 0000 C CNN F 1 "CONN_13X2" V 2400 1800 50 0000 C CNN
1 9600 1500 1 2400 1800
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L +5V #PWR01 L +3.3V #PWR01
U 1 1 501C4637 U 1 1 50A55B18
P 10100 800 P 1900 1050
F 0 "#PWR01" H 10100 890 20 0001 C CNN F 0 "#PWR01" H 1900 1010 30 0001 C CNN
F 1 "+5V" H 10100 890 30 0000 C CNN F 1 "+3.3V" H 1900 1160 30 0000 C CNN
1 10100 800 1 1900 1050
1 0 0 -1
$EndComp
$Comp
L +3.3V #PWR02
U 1 1 501C4646
P 9100 800
F 0 "#PWR02" H 9100 760 30 0001 C CNN
F 1 "+3.3V" H 9100 910 30 0000 C CNN
1 9100 800
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Wire Wire Line
1900 1050 1900 1200
Wire Wire Line
1900 1200 2000 1200
$Comp $Comp
L GND #PWR03 L +5V #PWR02
U 1 1 501C4659 U 1 1 50A55B2E
P 10100 2200 P 2900 1050
F 0 "#PWR03" H 10100 2200 30 0001 C CNN F 0 "#PWR02" H 2900 1140 20 0001 C CNN
F 1 "GND" H 10100 2130 30 0001 C CNN F 1 "+5V" H 2900 1140 30 0000 C CNN
1 10100 2200 1 2900 1050
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Wire Wire Line Wire Wire Line
10000 1100 10100 1100 2900 1050 2900 1200
Wire Wire Line Wire Wire Line
10100 1100 10100 2200 2900 1200 2800 1200
NoConn ~ 2800 1300
Wire Wire Line Wire Wire Line
10000 900 10100 900 2000 1300 1250 1300
Wire Wire Line Wire Wire Line
10100 900 10100 800 2000 1400 1250 1400
Text Label 1250 1300 0 60 ~ 0
GPIO0(SDA)
Text Label 1250 1400 0 60 ~ 0
GPIO1(SCL)
Wire Wire Line Wire Wire Line
9200 900 9100 900 2000 1500 1250 1500
Text Label 1250 1500 0 60 ~ 0
GPIO4
NoConn ~ 2000 1600
Wire Wire Line Wire Wire Line
9100 900 9100 800 2000 1700 1250 1700
Wire Wire Line Wire Wire Line
10000 1200 11000 1200 2000 1800 1250 1800
Wire Wire Line Wire Wire Line
10000 1300 11000 1300 2000 1900 1250 1900
Text Label 11000 1200 2 60 ~ 0 Text Label 1250 1700 0 60 ~ 0
GPIO14_(TxD) GPIO17
Text Label 11000 1300 2 60 ~ 0 Text Label 1250 1800 0 60 ~ 0
GPIO15_(RxD) GPIO21
Wire Wire Line Text Label 1250 1900 0 60 ~ 0
10000 1400 11000 1400 GPIO22
Text Label 11000 1400 2 60 ~ 0 NoConn ~ 2000 2000
GPIO18_(PCM_CLK)
Wire Wire Line
10000 1600 11000 1600
Wire Wire Line Wire Wire Line
10000 1700 11000 1700 2000 2100 1250 2100
Text Label 11000 1600 2 60 ~ 0
GPIO23
Text Label 11000 1700 2 60 ~ 0
GPIO24
Wire Wire Line Wire Wire Line
10000 1900 11000 1900 2000 2200 1250 2200
Wire Wire Line Wire Wire Line
10000 2000 11000 2000 2000 2300 1250 2300
Text Label 1250 2100 0 60 ~ 0
GPIO10(MOSI)
Text Label 1250 2200 0 60 ~ 0
GPIO9(MISO)
Text Label 1250 2300 0 60 ~ 0
GPIO11(SCLK)
NoConn ~ 2000 2400
$Comp
L GND #PWR03
U 1 1 50A55C3F
P 2900 2500
F 0 "#PWR03" H 2900 2500 30 0001 C CNN
F 1 "GND" H 2900 2430 30 0001 C CNN
1 2900 2500
1 0 0 -1
$EndComp
Wire Wire Line Wire Wire Line
10000 2100 11000 2100 2900 2500 2900 1400
Text Label 11000 1900 2 60 ~ 0
GPIO25
Text Label 11000 2000 2 60 ~ 0
GPIO8_(CE0)
Text Label 11000 2100 2 60 ~ 0
CPIO7_(CE1)
NoConn ~ 10000 1800
NoConn ~ 10000 1500
NoConn ~ 10000 1000
Wire Wire Line Wire Wire Line
9200 1000 8200 1000 2900 1400 2800 1400
Wire Wire Line Wire Wire Line
9200 1100 8200 1100 2800 1500 3500 1500
Wire Wire Line Wire Wire Line
9200 1200 8200 1200 2800 1600 3500 1600
Text Label 3500 1500 2 60 ~ 0
TXD
Text Label 3500 1600 2 60 ~ 0
RXD
Wire Wire Line Wire Wire Line
9200 1400 8200 1400 2800 1700 3500 1700
Text Label 3500 1700 2 60 ~ 0
GPIO18
NoConn ~ 2800 1800
Wire Wire Line Wire Wire Line
9200 1500 8200 1500 2800 1900 3500 1900
Wire Wire Line Wire Wire Line
9200 1600 8200 1600 2800 2000 3500 2000
Text Label 3500 1900 2 60 ~ 0
GPIO23
Text Label 3500 2000 2 60 ~ 0
GPIO24
NoConn ~ 2800 2100
Wire Wire Line Wire Wire Line
9200 1800 8200 1800 2800 2200 3500 2200
Text Label 3500 2200 2 60 ~ 0
GPIO25
Wire Wire Line Wire Wire Line
9200 1900 8200 1900 2800 2300 3500 2300
Wire Wire Line Wire Wire Line
9200 2000 8200 2000 2800 2400 3500 2400
NoConn ~ 9200 2100 Text Label 3500 2300 2 60 ~ 0
NoConn ~ 9200 1700 GPIO8(CE0)
NoConn ~ 9200 1300 Text Label 3500 2400 2 60 ~ 0
Text Label 8200 1000 0 60 ~ 0 GPIO7(CE1)
GPIO0_(SDA)
Text Label 8200 1100 0 60 ~ 0
GPIO1_(SCL)
Text Label 8200 1200 0 60 ~ 0
GPIO4_(GPCLK0)
Text Label 8200 1400 0 60 ~ 0
GPIO17
Text Label 8200 1500 0 60 ~ 0
GPIO21_(PCM_DOUT)
Text Label 8200 1600 0 60 ~ 0
GPIO22
Text Label 8200 1800 0 60 ~ 0
GPIO10_(MOSI)
Text Label 8200 1900 0 60 ~ 0
GPIO9_(MISO)
Text Label 8200 2000 0 60 ~ 0
GPIO11_(SCKL)
$EndSCHEMATC $EndSCHEMATC
template/raspberrypi-gpio/raspberrypi-gpio.stf 100644 → 100755
View file @ aaf6cce6
File mode changed from 100644 to 100755
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