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Commit 9b1eb354 authored by Maciej Suminski's avatar Maciej Suminski Committed by Wayne Stambaugh
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Pcbnew: fix OpenGL PNS router track not shown bug. (fixes lp:1275319)

parents 0e42a2ff 22201775
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Showing with 106 additions and 77 deletions
include/class_board_design_settings.h
View file @ 9b1eb354
......@@ -119,23 +119,25 @@ public:
* Function IsElementVisible
* tests whether a given element category is visible. Keep this as an
* inline function.
* @param aPCB_VISIBLE is from the enum by the same name
* @param aElementCategory is from the enum by the same name
* @return bool - true if the element is visible.
* @see enum PCB_VISIBLE
*/
bool IsElementVisible( int aPCB_VISIBLE ) const
bool IsElementVisible( int aElementCategory ) const
{
return bool( m_VisibleElements & (1 << aPCB_VISIBLE) );
assert( aElementCategory >= 0 && aElementCategory < END_PCB_VISIBLE_LIST );
return ( m_VisibleElements & ( 1 << aElementCategory ) );
}
/**
* Function SetElementVisibility
* changes the visibility of an element category
* @param aPCB_VISIBLE is from the enum by the same name
* @param aElementCategory is from the enum by the same name
* @param aNewState = The new visibility state of the element category
* @see enum PCB_VISIBLE
*/
void SetElementVisibility( int aPCB_VISIBLE, bool aNewState );
void SetElementVisibility( int aElementCategory, bool aNewState );
/**
* Function GetEnabledLayers
......
include/layers_id_colors_and_visibility.h
View file @ 9b1eb354
......@@ -239,8 +239,21 @@ enum PCB_VISIBLE
PADS_HOLES_VISIBLE,
VIAS_HOLES_VISIBLE,
// Netname layers
LAYER_1_NETNAMES_VISIBLE, // Bottom layer
WORKSHEET, ///< worksheet frame
GP_OVERLAY, ///< general purpose overlay
END_PCB_VISIBLE_LIST // sentinel
};
/**
* Enum NETNAMES_VISIBLE
* is a set of layers specific for displaying net names.
* Their visiblity is not supposed to be saved in a board file,
* they are only to be used by the GAL.
*/
enum NETNAMES_VISIBLE
{
LAYER_1_NETNAMES_VISIBLE, // bottom layer
LAYER_2_NETNAMES_VISIBLE,
LAYER_3_NETNAMES_VISIBLE,
LAYER_4_NETNAMES_VISIBLE,
......@@ -255,25 +268,22 @@ enum PCB_VISIBLE
LAYER_13_NETNAMES_VISIBLE,
LAYER_14_NETNAMES_VISIBLE,
LAYER_15_NETNAMES_VISIBLE,
LAYER_16_NETNAMES_VISIBLE, // Top layer
LAYER_16_NETNAMES_VISIBLE, // top layer
PAD_FR_NETNAMES_VISIBLE,
PAD_BK_NETNAMES_VISIBLE,
PADS_NETNAMES_VISIBLE,
WORKSHEET,
GP_OVERLAY, // General purpose overlay
END_PCB_VISIBLE_LIST // sentinel
END_NETNAMES_VISIBLE_LIST // sentinel
};
#define FIRST_NETNAME_LAYER ITEM_GAL_LAYER( LAYER_1_NETNAMES_VISIBLE )
#define LAST_NETNAME_LAYER ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE )
/// macro for obtaining layer number for specific item (eg. pad or text)
#define ITEM_GAL_LAYER(layer) (NB_LAYERS + layer)
#define ITEM_GAL_LAYER(layer) (NB_LAYERS + layer)
#define NETNAMES_GAL_LAYER(layer) (NB_LAYERS + END_PCB_VISIBLE_LIST + layer )
/// number of *all* layers including PCB and item layers
#define TOTAL_LAYER_COUNT 128 //(NB_LAYERS + END_PCB_VISIBLE_LIST)
#define TOTAL_LAYER_COUNT (NB_LAYERS + END_PCB_VISIBLE_LIST + END_NETNAMES_VISIBLE_LIST)
/**
* Function IsValidLayer
......@@ -390,30 +400,28 @@ wxString LayerMaskDescribe( const BOARD *aBoard, LAYER_MSK aMask );
inline LAYER_NUM GetNetnameLayer( LAYER_NUM aLayer )
{
if( IsCopperLayer( aLayer ) )
{
// Compute the offset in description layers
return FIRST_NETNAME_LAYER + ( aLayer - FIRST_COPPER_LAYER );
}
return NETNAMES_GAL_LAYER( aLayer );
else if( aLayer == ITEM_GAL_LAYER( PADS_VISIBLE ) )
return ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE );
return NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE );
else if( aLayer == ITEM_GAL_LAYER( PAD_FR_VISIBLE ) )
return ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE );
return NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE );
else if( aLayer == ITEM_GAL_LAYER( PAD_BK_VISIBLE ) )
return ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE );
return NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE );
// Fallback
return COMMENT_N;
}
/**
* Function IsCopperLayer
* Function IsNetnameLayer
* tests whether a layer is a netname layer
* @param aLayer = Layer to test
* @return true if aLayer is a valid netname layer
*/
inline bool IsNetnameLayer( LAYER_NUM aLayer )
{
return aLayer >= FIRST_NETNAME_LAYER && aLayer <= LAST_NETNAME_LAYER;
return aLayer >= NETNAMES_GAL_LAYER( LAYER_1_NETNAMES_VISIBLE ) &&
aLayer < NETNAMES_GAL_LAYER( END_NETNAMES_VISIBLE_LIST );
}
#endif // _LAYERS_ID_AND_VISIBILITY_H_
pcbnew/basepcbframe.cpp
View file @ 9b1eb354
......@@ -75,7 +75,7 @@ static const wxString FastGrid2Entry( wxT( "FastGrid2" ) );
const LAYER_NUM PCB_BASE_FRAME::GAL_LAYER_ORDER[] =
{
ITEM_GAL_LAYER( GP_OVERLAY ),
ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
DRAW_N, COMMENT_N, ECO1_N, ECO2_N, EDGE_N,
UNUSED_LAYER_29, UNUSED_LAYER_30, UNUSED_LAYER_31,
ITEM_GAL_LAYER( MOD_TEXT_FR_VISIBLE ),
......@@ -85,25 +85,25 @@ const LAYER_NUM PCB_BASE_FRAME::GAL_LAYER_ORDER[] =
ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),
ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ), SOLDERMASK_N_FRONT,
ITEM_GAL_LAYER( LAYER_16_NETNAMES_VISIBLE ), LAYER_N_FRONT,
NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ), SOLDERMASK_N_FRONT,
NETNAMES_GAL_LAYER( LAYER_16_NETNAMES_VISIBLE ), LAYER_N_FRONT,
SILKSCREEN_N_FRONT, SOLDERPASTE_N_FRONT, ADHESIVE_N_FRONT,
ITEM_GAL_LAYER( LAYER_15_NETNAMES_VISIBLE ), LAYER_N_15,
ITEM_GAL_LAYER( LAYER_14_NETNAMES_VISIBLE ), LAYER_N_14,
ITEM_GAL_LAYER( LAYER_13_NETNAMES_VISIBLE ), LAYER_N_13,
ITEM_GAL_LAYER( LAYER_12_NETNAMES_VISIBLE ), LAYER_N_12,
ITEM_GAL_LAYER( LAYER_11_NETNAMES_VISIBLE ), LAYER_N_11,
ITEM_GAL_LAYER( LAYER_10_NETNAMES_VISIBLE ), LAYER_N_10,
ITEM_GAL_LAYER( LAYER_9_NETNAMES_VISIBLE ), LAYER_N_9,
ITEM_GAL_LAYER( LAYER_8_NETNAMES_VISIBLE ), LAYER_N_8,
ITEM_GAL_LAYER( LAYER_7_NETNAMES_VISIBLE ), LAYER_N_7,
ITEM_GAL_LAYER( LAYER_6_NETNAMES_VISIBLE ), LAYER_N_6,
ITEM_GAL_LAYER( LAYER_5_NETNAMES_VISIBLE ), LAYER_N_5,
ITEM_GAL_LAYER( LAYER_4_NETNAMES_VISIBLE ), LAYER_N_4,
ITEM_GAL_LAYER( LAYER_3_NETNAMES_VISIBLE ), LAYER_N_3,
ITEM_GAL_LAYER( LAYER_2_NETNAMES_VISIBLE ), LAYER_N_2,
ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ), SOLDERMASK_N_BACK,
ITEM_GAL_LAYER( LAYER_1_NETNAMES_VISIBLE ), LAYER_N_BACK,
NETNAMES_GAL_LAYER( LAYER_15_NETNAMES_VISIBLE ), LAYER_N_15,
NETNAMES_GAL_LAYER( LAYER_14_NETNAMES_VISIBLE ), LAYER_N_14,
NETNAMES_GAL_LAYER( LAYER_13_NETNAMES_VISIBLE ), LAYER_N_13,
NETNAMES_GAL_LAYER( LAYER_12_NETNAMES_VISIBLE ), LAYER_N_12,
NETNAMES_GAL_LAYER( LAYER_11_NETNAMES_VISIBLE ), LAYER_N_11,
NETNAMES_GAL_LAYER( LAYER_10_NETNAMES_VISIBLE ), LAYER_N_10,
NETNAMES_GAL_LAYER( LAYER_9_NETNAMES_VISIBLE ), LAYER_N_9,
NETNAMES_GAL_LAYER( LAYER_8_NETNAMES_VISIBLE ), LAYER_N_8,
NETNAMES_GAL_LAYER( LAYER_7_NETNAMES_VISIBLE ), LAYER_N_7,
NETNAMES_GAL_LAYER( LAYER_6_NETNAMES_VISIBLE ), LAYER_N_6,
NETNAMES_GAL_LAYER( LAYER_5_NETNAMES_VISIBLE ), LAYER_N_5,
NETNAMES_GAL_LAYER( LAYER_4_NETNAMES_VISIBLE ), LAYER_N_4,
NETNAMES_GAL_LAYER( LAYER_3_NETNAMES_VISIBLE ), LAYER_N_3,
NETNAMES_GAL_LAYER( LAYER_2_NETNAMES_VISIBLE ), LAYER_N_2,
NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ), SOLDERMASK_N_BACK,
NETNAMES_GAL_LAYER( LAYER_1_NETNAMES_VISIBLE ), LAYER_N_BACK,
ADHESIVE_N_BACK, SOLDERPASTE_N_BACK, SILKSCREEN_N_BACK,
ITEM_GAL_LAYER( MOD_TEXT_BK_VISIBLE ),
......@@ -793,14 +793,14 @@ void PCB_BASE_FRAME::LoadSettings()
// Some more required layers settings
view->SetRequired( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( VIAS_VISIBLE ) );
view->SetRequired( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
view->SetRequired( ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
view->SetRequired( NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
view->SetRequired( ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetRequired( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetRequired( ADHESIVE_N_FRONT, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetRequired( SOLDERPASTE_N_FRONT, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetRequired( SOLDERMASK_N_FRONT, ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetRequired( ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
view->SetRequired( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
view->SetRequired( ADHESIVE_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
view->SetRequired( SOLDERPASTE_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
view->SetRequired( SOLDERMASK_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
......
pcbnew/class_board_design_settings.cpp
View file @ 9b1eb354
......@@ -243,3 +243,16 @@ void BOARD_DESIGN_SETTINGS::SetEnabledLayers( LAYER_MSK aMask )
// update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
m_CopperLayerCount = LayerMaskCountSet( aMask & ALL_CU_LAYERS);
}
#ifndef NDEBUG
struct static_check {
static_check()
{
// Int (the type used for saving visibility settings) is only 32 bits guaranteed,
// be sure that we do not cross the limit
assert( END_PCB_VISIBLE_LIST <= 32 );
};
};
static static_check check;
#endif
pcbnew/class_pad.cpp
View file @ 9b1eb354
......@@ -841,7 +841,7 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
{
// Multi layer pad
aLayers[aCount++] = ITEM_GAL_LAYER( PADS_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE );
aLayers[aCount++] = NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE );
aLayers[aCount++] = SOLDERMASK_N_FRONT;
aLayers[aCount++] = SOLDERMASK_N_BACK;
aLayers[aCount++] = SOLDERPASTE_N_FRONT;
......@@ -850,14 +850,14 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const
else if( IsOnLayer( LAYER_N_FRONT ) )
{
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE );
aLayers[aCount++] = NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE );
aLayers[aCount++] = SOLDERMASK_N_FRONT;
aLayers[aCount++] = SOLDERPASTE_N_FRONT;
}
else if( IsOnLayer( LAYER_N_BACK ) )
{
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_VISIBLE );
aLayers[aCount++] = ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE );
aLayers[aCount++] = NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE );
aLayers[aCount++] = SOLDERMASK_N_BACK;
aLayers[aCount++] = SOLDERPASTE_N_BACK;
}
......
pcbnew/class_track.cpp
View file @ 9b1eb354
......@@ -763,9 +763,9 @@ void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const
unsigned int TRACK::ViewGetLOD( int aLayer ) const
{
// Netnames will be shown only if zoom is appropriate
if( aLayer == GetNetnameLayer( GetLayer() ) )
if( IsNetnameLayer( aLayer ) )
{
return ( 20000000 / m_Width );
return ( 20000000 / ( m_Width + 1 ) );
}
// Other layers are shown without any conditions
......
pcbnew/pcb_painter.cpp
View file @ 9b1eb354
......@@ -68,14 +68,14 @@ void PCB_RENDER_SETTINGS::ImportLegacyColors( COLORS_DESIGN_SETTINGS* aSettings
}
// Default colors for specific layers
m_layerColors[ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE )] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
m_layerColors[ITEM_GAL_LAYER( PADS_HOLES_VISIBLE )] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
m_layerColors[ITEM_GAL_LAYER( VIAS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_layerColors[ITEM_GAL_LAYER( PADS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_layerColors[ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[ITEM_GAL_LAYER( WORKSHEET )] = COLOR4D( 0.5, 0.0, 0.0, 1.0 );
m_layerColors[ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE )] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
m_layerColors[ITEM_GAL_LAYER( PADS_HOLES_VISIBLE )] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
m_layerColors[ITEM_GAL_LAYER( VIAS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_layerColors[ITEM_GAL_LAYER( PADS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
m_layerColors[NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
m_layerColors[ITEM_GAL_LAYER( WORKSHEET )] = COLOR4D( 0.5, 0.0, 0.0, 1.0 );
// Netnames for copper layers
for( LAYER_NUM layer = FIRST_COPPER_LAYER; layer <= LAST_COPPER_LAYER; ++layer )
......@@ -261,13 +261,14 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
VECTOR2D start( aTrack->GetStart() );
VECTOR2D end( aTrack->GetEnd() );
int width = aTrack->GetWidth();
int netNumber = aTrack->GetNet();
COLOR4D color;
if( m_pcbSettings->m_netNamesOnTracks && IsNetnameLayer( aLayer ) )
{
int netCode = aTrack->GetNet();
// If there is a net name - display it on the track
if( netNumber > 0 )
if( netCode > 0 )
{
VECTOR2D line = ( end - start );
double length = line.EuclideanNorm();
......@@ -276,11 +277,11 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
if( length < 10 * width )
return;
NETINFO_ITEM* net = ( (BOARD*) aTrack->GetParent() )->FindNet( netNumber );
NETINFO_ITEM* net = ( (BOARD*) aTrack->GetParent() )->FindNet( netCode );
if( !net )
return;
std::wstring netName = std::wstring( net->GetShortNetname().wc_str() );
wxString netName = net->GetShortNetname();
VECTOR2D textPosition = start + line / 2.0; // center of the track
double textOrientation = -atan( line.y / line.x );
double textSize = std::min( static_cast<double>( width ), length / netName.length() );
......@@ -304,7 +305,7 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer )
m_gal->StrokeText( netName, textPosition, textOrientation );
}
}
else if( IsCopperLayer( aLayer ))
else if( IsCopperLayer( aLayer ) )
{
// Draw a regular track
color = m_pcbSettings->GetColor( aTrack, aLayer );
......
pcbnew/pcb_painter.h
View file @ 9b1eb354
......@@ -114,6 +114,7 @@ protected:
///> Colors for all layers (darkened)
COLOR4D m_layerColorsDark[TOTAL_LAYER_COUNT];
///> Flag determining if items on a given layer should be drawn as an outline or a full item
bool m_sketchModeSelect[TOTAL_LAYER_COUNT];
///> Flag determining if pad numbers should be visible
......
pcbnew/pcbframe.cpp
View file @ 9b1eb354
......@@ -916,7 +916,7 @@ void PCB_EDIT_FRAME::setHighContrastLayer( LAYER_NUM aLayer )
LAYER_NUM layers[] = {
GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIAS_VISIBLE ),
ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE )
};
......@@ -927,12 +927,12 @@ void PCB_EDIT_FRAME::setHighContrastLayer( LAYER_NUM aLayer )
if( aLayer == FIRST_COPPER_LAYER )
{
rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
rSettings->SetActiveLayer( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
}
else if( aLayer == LAST_COPPER_LAYER )
{
rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
rSettings->SetActiveLayer( ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
rSettings->SetActiveLayer( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
}
}
......@@ -956,7 +956,7 @@ void PCB_EDIT_FRAME::setTopLayer( LAYER_NUM aLayer )
LAYER_NUM layers[] = {
GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIAS_VISIBLE ),
ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE ), DRAW_N
};
......@@ -969,12 +969,12 @@ void PCB_EDIT_FRAME::setTopLayer( LAYER_NUM aLayer )
if( aLayer == FIRST_COPPER_LAYER )
{
view->SetTopLayer( ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
view->SetTopLayer( ITEM_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
view->SetTopLayer( NETNAMES_GAL_LAYER( PAD_BK_NETNAMES_VISIBLE ) );
}
else if( aLayer == LAST_COPPER_LAYER )
{
view->SetTopLayer( ITEM_GAL_LAYER( PAD_FR_VISIBLE ) );
view->SetTopLayer( ITEM_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
view->SetTopLayer( NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ) );
}
}
......@@ -1014,10 +1014,15 @@ void PCB_EDIT_FRAME::syncLayerVisibilities()
m_Layers->SyncLayerVisibilities();
KIGFX::VIEW* view = GetGalCanvas()->GetView();
// Load layer & elements visibility settings
for( LAYER_NUM i = 0; i < NB_LAYERS; ++i )
{
view->SetLayerVisible( i, m_Pcb->IsLayerVisible( i ) );
// Synchronize netname layers as well
if( IsCopperLayer( i ) )
view->SetLayerVisible( GetNetnameLayer( i ), m_Pcb->IsLayerVisible( i ) );
}
for( LAYER_NUM i = 0; i < END_PCB_VISIBLE_LIST; ++i )
......@@ -1026,12 +1031,10 @@ void PCB_EDIT_FRAME::syncLayerVisibilities()
}
// Enable some layers that are GAL specific
for( LAYER_NUM i = FIRST_NETNAME_LAYER; i < LAST_NETNAME_LAYER; ++i )
{
view->SetLayerVisible( i, true );
}
view->SetLayerVisible( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), true );
view->SetLayerVisible( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), true );
view->SetLayerVisible( ITEM_GAL_LAYER( WORKSHEET ), true );
view->SetLayerVisible( ITEM_GAL_LAYER( GP_OVERLAY ), true );
}
......
pcbnew/router/router_preview_item.cpp
View file @ 9b1eb354
......@@ -36,6 +36,7 @@ ROUTER_PREVIEW_ITEM::ROUTER_PREVIEW_ITEM( const PNS_ITEM* aItem, VIEW_GROUP* aPa
{
m_Flags = 0;
m_parent = aParent;
m_layer = DRAW_N;
if( aItem )
Update( aItem );
......
pcbnew/router/router_preview_item.h
View file @ 9b1eb354
......@@ -73,7 +73,7 @@ public:
virtual void ViewGetLayers( int aLayers[], int& aCount ) const
{
aLayers[0] = GP_OVERLAY;
aLayers[0] = m_layer;
aCount = 1;
}
......
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