Added a few settings to make the layer settings more similar to KiCad defaults... (54bf2176) · Commits · Elphel / kicad-source-mirror

common/view/view.cpp

+12 −1

Original line number	Original line	Diff line number	Diff line
	@@ -765,6 +765,11 @@ void VIEW::ClearTargets()

	void VIEW::Redraw()		void VIEW::Redraw()
	{		{
			#ifdef PROFILE
			prof_counter totalRealTime;
			prof_start( &totalRealTime );
			#endif /* PROFILE */

	VECTOR2D screenSize = m_gal->GetScreenPixelSize();		VECTOR2D screenSize = m_gal->GetScreenPixelSize();
	BOX2I rect( ToWorld( VECTOR2D( 0, 0 ) ),		BOX2I rect( ToWorld( VECTOR2D( 0, 0 ) ),
	ToWorld( screenSize ) - ToWorld( VECTOR2D( 0, 0 ) ) );		ToWorld( screenSize ) - ToWorld( VECTOR2D( 0, 0 ) ) );
	@@ -776,6 +781,12 @@ void VIEW::Redraw()
	markTargetClean( TARGET_CACHED );		markTargetClean( TARGET_CACHED );
	markTargetClean( TARGET_NONCACHED );		markTargetClean( TARGET_NONCACHED );
	markTargetClean( TARGET_OVERLAY );		markTargetClean( TARGET_OVERLAY );

			#ifdef PROFILE
			prof_end( &totalRealTime );

			wxLogDebug( wxT( "Redraw: %.1f ms" ), totalRealTime.msecs() );
			#endif /* PROFILE */
	}		}


	@@ -971,7 +982,7 @@ bool VIEW::areRequiredLayersEnabled( int aLayerId ) const
	it_end = m_layers.at( aLayerId ).requiredLayers.end(); it != it_end; ++it )		it_end = m_layers.at( aLayerId ).requiredLayers.end(); it != it_end; ++it )
	{		{
	// That is enough if just one layer is not enabled		// That is enough if just one layer is not enabled
	if( !m_layers.at( *it ).visible )		if( !m_layers.at( it ).visible \|\| !areRequiredLayersEnabled( it ) )
	return false;		return false;
	}		}

pcbnew/basepcbframe.cpp

+5 −2

pcbnew/class_track.cpp

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -981,7 +981,7 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
	void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const		void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const
	{		{
	// Just show it on common via & via holes layers		// Just show it on common via & via holes layers
	aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE );		aLayers[0] = ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE );
	aLayers[1] = ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE );		aLayers[1] = ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE );
	aCount = 2;		aCount = 2;
	}		}

pcbnew/pcb_painter.cpp

+6 −6

pcbnew/pcbframe.cpp

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -83,7 +83,7 @@ const LAYER_NUM PCB_BASE_FRAME::GAL_LAYER_ORDER[] =

	ITEM_GAL_LAYER( RATSNEST_VISIBLE ),		ITEM_GAL_LAYER( RATSNEST_VISIBLE ),
	ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),		ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ),
	ITEM_GAL_LAYER( VIAS_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),		ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),

	NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ), SOLDERMASK_N_FRONT,		NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PAD_FR_VISIBLE ), SOLDERMASK_N_FRONT,
	NETNAMES_GAL_LAYER( LAYER_16_NETNAMES_VISIBLE ), LAYER_N_FRONT,		NETNAMES_GAL_LAYER( LAYER_16_NETNAMES_VISIBLE ), LAYER_N_FRONT,
	@@ -798,7 +798,7 @@ void PCB_BASE_FRAME::LoadSettings()
	}		}

	// Some more required layers settings		// Some more required layers settings
	view->SetRequired( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( VIAS_VISIBLE ) );		view->SetRequired( ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ) );
	view->SetRequired( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );		view->SetRequired( ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );
	view->SetRequired( NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );		view->SetRequired( NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ) );

	@@ -812,6 +812,9 @@ void PCB_BASE_FRAME::LoadSettings()
	view->SetRequired( SOLDERPASTE_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );		view->SetRequired( SOLDERPASTE_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );
	view->SetRequired( SOLDERMASK_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );		view->SetRequired( SOLDERMASK_N_BACK, ITEM_GAL_LAYER( PAD_BK_VISIBLE ) );

			view->SetRequired( ITEM_GAL_LAYER( PAD_FR_VISIBLE ), ITEM_GAL_LAYER( MOD_FR_VISIBLE ) );
			view->SetRequired( ITEM_GAL_LAYER( PAD_BK_VISIBLE ), ITEM_GAL_LAYER( MOD_BK_VISIBLE ) );

	view->SetLayerTarget( ITEM_GAL_LAYER( GP_OVERLAY ), KIGFX::TARGET_OVERLAY );		view->SetLayerTarget( ITEM_GAL_LAYER( GP_OVERLAY ), KIGFX::TARGET_OVERLAY );
	view->SetLayerTarget( ITEM_GAL_LAYER( RATSNEST_VISIBLE ), KIGFX::TARGET_OVERLAY );		view->SetLayerTarget( ITEM_GAL_LAYER( RATSNEST_VISIBLE ), KIGFX::TARGET_OVERLAY );

Original line number	Original line	Diff line number	Diff line
	@@ -69,7 +69,7 @@ void PCB_RENDER_SETTINGS::ImportLegacyColors( COLORS_DESIGN_SETTINGS* aSettings
	// Default colors for specific layers		// Default colors for specific layers
	m_layerColors[ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE )] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );		m_layerColors[ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE )] = COLOR4D( 0.5, 0.4, 0.0, 1.0 );
	m_layerColors[ITEM_GAL_LAYER( PADS_HOLES_VISIBLE )] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );		m_layerColors[ITEM_GAL_LAYER( PADS_HOLES_VISIBLE )] = COLOR4D( 0.0, 0.5, 0.5, 1.0 );
	m_layerColors[ITEM_GAL_LAYER( VIAS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );		m_layerColors[ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
	m_layerColors[ITEM_GAL_LAYER( PADS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );		m_layerColors[ITEM_GAL_LAYER( PADS_VISIBLE )] = COLOR4D( 0.7, 0.7, 0.7, 1.0 );
	m_layerColors[NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );		m_layerColors[NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
	m_layerColors[NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );		m_layerColors[NETNAMES_GAL_LAYER( PAD_FR_NETNAMES_VISIBLE )] = COLOR4D( 0.8, 0.8, 0.8, 0.7 );
	@@ -95,7 +95,7 @@ void PCB_RENDER_SETTINGS::LoadDisplayOptions( const DISPLAY_OPTIONS& aOptions )

	// Whether to draw tracks, vias & pads filled or as outlines		// Whether to draw tracks, vias & pads filled or as outlines
	m_sketchModeSelect[PADS_VISIBLE] = !aOptions.DisplayPadFill;		m_sketchModeSelect[PADS_VISIBLE] = !aOptions.DisplayPadFill;
	m_sketchModeSelect[VIAS_VISIBLE] = !aOptions.DisplayViaFill;		m_sketchModeSelect[VIA_THROUGH_VISIBLE] = !aOptions.DisplayViaFill;
	m_sketchModeSelect[TRACKS_VISIBLE] = !aOptions.DisplayPcbTrackFill;		m_sketchModeSelect[TRACKS_VISIBLE] = !aOptions.DisplayPcbTrackFill;

	switch( aOptions.DisplayNetNamesMode )		switch( aOptions.DisplayNetNamesMode )
	@@ -328,7 +328,7 @@ void PCB_PAINTER::draw( const SEGVIA* aVia, int aLayer )
	double radius;		double radius;

	// Choose drawing settings depending on if we are drawing via's pad or hole		// Choose drawing settings depending on if we are drawing via's pad or hole
	if( aLayer == ITEM_GAL_LAYER( VIAS_VISIBLE ) )		if( aLayer == ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ) )
	{		{
	radius = aVia->GetWidth() / 2.0;		radius = aVia->GetWidth() / 2.0;
	}		}
	@@ -341,7 +341,7 @@ void PCB_PAINTER::draw( const SEGVIA* aVia, int aLayer )

	const COLOR4D& color = m_pcbSettings->GetColor( aVia, aLayer );		const COLOR4D& color = m_pcbSettings->GetColor( aVia, aLayer );

	if( m_pcbSettings->m_sketchModeSelect[VIAS_VISIBLE] )		if( m_pcbSettings->m_sketchModeSelect[VIA_THROUGH_VISIBLE] )
	{		{
	// Outline mode		// Outline mode
	m_gal->SetIsFill( false );		m_gal->SetIsFill( false );

Original line number	Original line	Diff line number	Diff line
	@@ -879,7 +879,7 @@ void PCB_EDIT_FRAME::setHighContrastLayer( LAYER_NUM aLayer )
	// fixme do not like the idea of storing the list of layers here,		// fixme do not like the idea of storing the list of layers here,
	// should be done in some other way I guess..		// should be done in some other way I guess..
	LAYER_NUM layers[] = {		LAYER_NUM layers[] = {
	GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIAS_VISIBLE ),		GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ),
	ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),		ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
	ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),		ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
	ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE )		ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE )
	@@ -919,7 +919,7 @@ void PCB_EDIT_FRAME::SetTopLayer( LAYER_NUM aLayer )
	// fixme do not like the idea of storing the list of layers here,		// fixme do not like the idea of storing the list of layers here,
	// should be done in some other way I guess..		// should be done in some other way I guess..
	LAYER_NUM layers[] = {		LAYER_NUM layers[] = {
	GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIAS_VISIBLE ),		GetNetnameLayer( aLayer ), ITEM_GAL_LAYER( VIA_THROUGH_VISIBLE ),
	ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),		ITEM_GAL_LAYER( VIAS_HOLES_VISIBLE ), ITEM_GAL_LAYER( PADS_VISIBLE ),
	ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),		ITEM_GAL_LAYER( PADS_HOLES_VISIBLE ), NETNAMES_GAL_LAYER( PADS_NETNAMES_VISIBLE ),
	ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE ), DRAW_N		ITEM_GAL_LAYER( GP_OVERLAY ), ITEM_GAL_LAYER( RATSNEST_VISIBLE ), DRAW_N

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