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Commit 4c2a1dd5 authored by Dick Hollenbeck's avatar Dick Hollenbeck
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more kicad_plugin work, make BOARD::m_NetInfo private

parent a67ff643
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.bzrignore
View file @ 4c2a1dd5
......@@ -17,8 +17,8 @@ install_manifest.txt
Documentation/doxygen
*.cmake
*.bak
pcbnew/pcb_plot_params_keywords.cpp
pcbnew/pcb_plot_params_lexer.h
common/pcb_plot_params_keywords.cpp
common/pcb_plot_params_lexer.h
pcbnew/specctra_keywords.cpp
pcbnew/specctra_lexer.h
new/html
......
CHANGELOG.txt
View file @ 4c2a1dd5
......@@ -4,6 +4,14 @@ KiCad ChangeLog 2011
Please add newer entries at the top, list the date and your name with
email address.
2011-Dec-9 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
++PCBNew
* added BOARD::GetPad(int), made BOARD::m_NetInfo private
* more kicad_plugin work.
2011-Dec-5 UPDATE Dick Hollenbeck <dick@softplc.com>
================================================================================
++PCBNew
......
CMakeLists.txt
View file @ 4c2a1dd5
......@@ -276,9 +276,13 @@ add_subdirectory(template)
#================================================
find_package(Doxygen)
if(DOXYGEN_FOUND)
add_custom_target( doxygen-docs ${DOXYGEN_EXECUTABLE}
add_custom_target( doxygen-docs
${CMAKE_COMMAND} -E remove_directory Documentation/doxygen
COMMAND ${DOXYGEN_EXECUTABLE}
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
DEPENDS Doxyfile )
DEPENDS Doxyfile
COMMENT "building doxygen docs into directory Documentation/doxygen/html"
)
else(DOXYGEN_FOUND)
message( STATUS "WARNING: Doxygen not found - doxygen-docs (Source Docs) target not created" )
endif()
......
include/dlist.h
View file @ 4c2a1dd5
......@@ -113,7 +113,7 @@ public:
* Function GetCount
* returns the number of elements in the list.
*/
unsigned GetCount() { return count; }
unsigned GetCount() const { return count; }
#if defined(DEBUG)
void VerifyListIntegrity();
......
pcbnew/board.cpp
View file @ 4c2a1dd5
......@@ -203,9 +203,9 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag )
via_marge = clearance + (viaSize / 2);
// Place PADS on matrix routing:
for( unsigned i = 0; i < aPcb->GetPadsCount(); ++i )
for( unsigned i = 0; i < aPcb->GetPadCount(); ++i )
{
D_PAD* pad = aPcb->m_NetInfo->GetPad( i );
D_PAD* pad = aPcb->GetPad( i );
if( net_code != pad->GetNet() || (flag & FORCE_PADS) )
{
......
pcbnew/class_board.cpp
View file @ 4c2a1dd5
......@@ -30,6 +30,7 @@ wxPoint BOARD_ITEM::ZeroOffset( 0, 0 );
BOARD::BOARD() :
BOARD_ITEM( (BOARD_ITEM*) NULL, PCB_T ),
m_NetInfo( this ),
m_NetClasses( this )
{
// we have not loaded a board yet, assume latest until then.
......@@ -42,8 +43,8 @@ BOARD::BOARD() :
m_CurrentZoneContour = NULL; // This ZONE_CONTAINER handle the
// zone contour currently in progress
m_NetInfo = new NETINFO_LIST( this ); // handle nets info list (name, design constraints ..
m_NetInfo->BuildListOfNets(); // prepare pads and nets lists containers.
BuildListOfNets(); // prepare pad and netlist containers.
for( int layer = 0; layer < NB_COPPER_LAYERS; ++layer )
{
......@@ -89,8 +90,6 @@ BOARD::~BOARD()
delete m_CurrentZoneContour;
m_CurrentZoneContour = NULL;
delete m_NetInfo;
}
......@@ -814,25 +813,25 @@ void BOARD::DeleteZONEOutlines()
}
int BOARD::GetNumSegmTrack()
int BOARD::GetNumSegmTrack() const
{
return m_Track.GetCount();
}
int BOARD::GetNumSegmZone()
int BOARD::GetNumSegmZone() const
{
return m_Zone.GetCount();
}
unsigned BOARD::GetNoconnectCount()
unsigned BOARD::GetNoconnectCount() const
{
return m_NbNoconnect;
}
unsigned BOARD::GetNodesCount()
unsigned BOARD::GetNodesCount() const
{
return m_NbNodes;
}
......@@ -844,7 +843,7 @@ EDA_RECT BOARD::ComputeBoundingBox( bool aBoardEdgesOnly )
EDA_RECT area;
// Check segments, dimensions, texts, and fiducials
for( BOARD_ITEM* item = m_Drawings; item != NULL; item = item->Next() )
for( BOARD_ITEM* item = m_Drawings; item; item = item->Next() )
{
if( aBoardEdgesOnly && (item->Type() != PCB_LINE_T || item->GetLayer() != EDGE_N ) )
continue;
......@@ -931,7 +930,7 @@ void BOARD::DisplayInfo( EDA_DRAW_FRAME* frame )
trackSegmentsCount++;
}
txt.Printf( wxT( "%d" ), GetPadsCount() );
txt.Printf( wxT( "%d" ), GetPadCount() );
frame->AppendMsgPanel( _( "Pads" ), txt, DARKGREEN );
txt.Printf( wxT( "%d" ), viasCount );
......@@ -943,7 +942,7 @@ void BOARD::DisplayInfo( EDA_DRAW_FRAME* frame )
txt.Printf( wxT( "%d" ), GetNodesCount() );
frame->AppendMsgPanel( _( "Nodes" ), txt, DARKCYAN );
txt.Printf( wxT( "%d" ), m_NetInfo->GetCount() );
txt.Printf( wxT( "%d" ), m_NetInfo.GetNetCount() );
frame->AppendMsgPanel( _( "Nets" ), txt, RED );
/* These parameters are known only if the full ratsnest is available,
......@@ -1229,10 +1228,10 @@ SEARCH_RESULT BOARD::Visit( INSPECTOR* inspector, const void* testData,
NETINFO_ITEM* BOARD::FindNet( int aNetcode ) const
{
// the first valid netcode is 1 and the last is m_NetInfo->GetCount()-1.
// the first valid netcode is 1 and the last is m_NetInfo.GetCount()-1.
// zero is reserved for "no connection" and is not used.
// NULL is returned for non valid netcodes
NETINFO_ITEM* net = m_NetInfo->GetNetItem( aNetcode );
NETINFO_ITEM* net = m_NetInfo.GetNetItem( aNetcode );
#if defined(DEBUG)
if( net ) // item can be NULL if anetcode is not valid
......@@ -1256,7 +1255,7 @@ NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname ) const
if( aNetname.IsEmpty() )
return NULL;
int ncount = m_NetInfo->GetCount();
int ncount = m_NetInfo.GetNetCount();
// Search for a netname = aNetname
#if 0
......@@ -1264,7 +1263,7 @@ NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname ) const
// Use a sequential search: easy to understand, but slow
for( int ii = 1; ii < ncount; ii++ )
{
NETINFO_ITEM* item = m_NetInfo->GetNetItem( ii );
NETINFO_ITEM* item = m_NetInfo.GetNetItem( ii );
if( item && item->GetNetname() == aNetname )
{
......@@ -1289,7 +1288,7 @@ NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname ) const
if( (ii & 1) && ( ii > 1 ) )
ncount++;
NETINFO_ITEM* item = m_NetInfo->GetNetItem( index );
NETINFO_ITEM* item = m_NetInfo.GetNetItem( index );
if( item == NULL )
return NULL;
......@@ -1370,18 +1369,18 @@ static bool s_SortByNodes( const NETINFO_ITEM* a, const NETINFO_ITEM* b )
int BOARD::ReturnSortedNetnamesList( wxArrayString& aNames, bool aSortbyPadsCount )
{
if( m_NetInfo->GetCount() == 0 )
if( m_NetInfo.GetNetCount() == 0 )
return 0;
// Build the list
std::vector <NETINFO_ITEM*> netBuffer;
netBuffer.reserve( m_NetInfo->GetCount() );
netBuffer.reserve( m_NetInfo.GetNetCount() );
for( unsigned ii = 1; ii < m_NetInfo->GetCount(); ii++ )
for( unsigned ii = 1; ii < m_NetInfo.GetNetCount(); ii++ )
{
if( m_NetInfo->GetNetItem( ii )->GetNet() > 0 )
netBuffer.push_back( m_NetInfo->GetNetItem( ii ) );
if( m_NetInfo.GetNetItem( ii )->GetNet() > 0 )
netBuffer.push_back( m_NetInfo.GetNetItem( ii ) );
}
// sort the list
......@@ -1561,9 +1560,9 @@ D_PAD* BOARD::GetPad( TRACK* aTrace, int aEndPoint )
D_PAD* BOARD::GetPadFast( const wxPoint& aPosition, int aLayerMask )
{
for( unsigned i=0; i<GetPadsCount(); ++i )
for( unsigned i=0; i<GetPadCount(); ++i )
{
D_PAD* pad = m_NetInfo->GetPad(i);
D_PAD* pad = m_NetInfo.GetPad(i);
if( pad->m_Pos != aPosition )
continue;
......@@ -1675,8 +1674,8 @@ static bool sortPadsByXthenYCoord( D_PAD* const & ref, D_PAD* const & comp )
void BOARD::GetSortedPadListByXthenYCoord( std::vector<D_PAD*>& aVector )
{
aVector.insert( aVector.end(), m_NetInfo->m_PadsFullList.begin(),
m_NetInfo->m_PadsFullList.end() );
aVector.insert( aVector.end(), m_NetInfo.m_PadsFullList.begin(),
m_NetInfo.m_PadsFullList.end() );
sort( aVector.begin(), aVector.end(), sortPadsByXthenYCoord );
}
......
pcbnew/class_board.h
View file @ 4c2a1dd5
......@@ -38,7 +38,8 @@ typedef std::vector< TRACK* > TRACK_PTRS;
* Enum LAYER_T
* gives the allowed types of layers, same as Specctra DSN spec.
*/
enum LAYER_T {
enum LAYER_T
{
LT_SIGNAL,
LT_POWER,
LT_MIXED,
......@@ -169,6 +170,23 @@ private:
EDA_RECT m_BoundingBox;
NETINFO_LIST m_NetInfo; ///< net info list (name, design constraints ..
BOARD_DESIGN_SETTINGS m_designSettings;
COLORS_DESIGN_SETTINGS* m_colorsSettings; // Link to current colors settings
/**
* Function chainMarkedSegments
* is used by MarkTrace() to set the BUSY flag of connected segments of the trace
* segment located at \a aPosition on aLayerMask.
* Vias are put in list but their flags BUSY is not set
* @param aPosition A wxPoint object containing the position of the starting search.
* @param aLayerMask The allowed layers for segments to search.
* @param aList The track list to fill with points of flagged segments.
*/
void chainMarkedSegments( wxPoint aPosition, int aLayerMask, TRACK_PTRS* aList );
public:
/// Flags used in ratsnest calculation and update.
......@@ -185,9 +203,6 @@ public:
DLIST<TRACK> m_Track; // linked list of TRACKs and SEGVIAs
DLIST<SEGZONE> m_Zone; // linked list of SEGZONEs
/// nets info list (name, design constraints ..
NETINFO_LIST* m_NetInfo;
/// Ratsnest list for the BOARD
std::vector<RATSNEST_ITEM> m_FullRatsnest;
......@@ -223,22 +238,7 @@ public:
// Index for m_TrackWidthList to select the value.
unsigned m_TrackWidthSelector;
private:
BOARD_DESIGN_SETTINGS m_designSettings;
COLORS_DESIGN_SETTINGS* m_colorsSettings; // Link to current colors settings
/**
* Function chainMarkedSegments
* is used by MarkTrace() to set the BUSY flag of connected segments of the trace
* segment located at \a aPosition on aLayerMask.
* Vias are put in list but their flags BUSY is not set
* @param aPosition A wxPoint object containing the position of the starting search.
* @param aLayerMask The allowed layers for segments to search.
* @param aList The track list to fill with points of flagged segments.
*/
void chainMarkedSegments( wxPoint aPosition, int aLayerMask, TRACK_PTRS* aList );
public:
BOARD();
~BOARD();
......@@ -310,7 +310,6 @@ public:
*/
void DeleteZONEOutlines();
/**
* Function GetMARKER
* returns the MARKER at a given index.
......@@ -325,7 +324,6 @@ public:
return NULL;
}
/**
* Function GetMARKERCount
* @return int - The number of MARKER_PCBS.
......@@ -335,7 +333,6 @@ public:
return (int) m_markers.size();
}
/**
* Function ResetHighLight
* Reset all high light data to the init state
......@@ -361,7 +358,6 @@ public:
m_hightLight.m_netCode = aNetCode;
}
/**
* Function IsHighLightNetON
* @return true if a net is currently highlighted
......@@ -610,19 +606,19 @@ public:
*/
int GetLayerColor( int aLayer );
/* Functions to get some items count */
int GetNumSegmTrack();
/** Functions to get some items count */
int GetNumSegmTrack() const;
/* Calculate the zone segment count */
int GetNumSegmZone();
/** Calculate the zone segment count */
int GetNumSegmZone() const;
unsigned GetNoconnectCount(); // Return the number of missing links.
unsigned GetNoconnectCount() const; // Return the number of missing links.
/**
* Function GetNumRatsnests
* @return int - The number of rats
*/
unsigned GetRatsnestsCount()
unsigned GetRatsnestsCount() const
{
return m_FullRatsnest.size();
}
......@@ -632,15 +628,71 @@ public:
* Function GetNodesCount
* @return the number of pads members of nets (i.e. with netcode > 0)
*/
unsigned GetNodesCount();
unsigned GetNodesCount() const;
/**
* Function GetPadsCount
* Function GetPadCount
* @return the number of pads in board
*/
unsigned GetPadsCount()
unsigned GetPadCount() const
{
return m_NetInfo.GetPadCount();
}
/**
* Function GetPad
* @return D_PAD* - at the \a aIndex from m_NetInfo
*/
D_PAD* GetPad( unsigned aIndex ) const
{
return m_NetInfo.GetPad( aIndex );
}
/**
* Function GetPads
* returns a list of all the pads by value. The returned list is not
* sorted and contains pointers to PADS, but those pointers do not convey
* ownership of the respective PADs.
* @return std::vector<D_PAD*> - a full list of pads
*/
std::vector<D_PAD*> GetPads()
{
return m_NetInfo.m_PadsFullList;
}
void BuildListOfNets()
{
m_NetInfo.buildListOfNets();
}
/**
* Function FindNet
* searches for a net with the given netcode.
* @param aNetcode A netcode to search for.
* @return NETINFO_ITEM_ITEM* - the net or NULL if not found.
*/
NETINFO_ITEM* FindNet( int aNetcode ) const;
/**
* Function FindNet overloaded
* searches for a net with the given name.
* @param aNetname A Netname to search for.
* @return NETINFO_ITEM* - the net or NULL if not found.
*/
NETINFO_ITEM* FindNet( const wxString& aNetname ) const;
void AppendNet( NETINFO_ITEM* aNewNet )
{
m_NetInfo.AppendNet( aNewNet );
}
/**
* Function GetNetCount
* @return the number of nets (NETINFO_ITEM)
*/
unsigned GetNetCount() const
{
return m_NetInfo->GetPadsCount();
return m_NetInfo.GetNetCount();
}
/**
......@@ -709,23 +761,6 @@ public:
SEARCH_RESULT Visit( INSPECTOR* inspector, const void* testData,
const KICAD_T scanTypes[] );
/**
* Function FindNet
* searches for a net with the given netcode.
* @param aNetcode A netcode to search for.
* @return NETINFO_ITEM_ITEM* - the net or NULL if not found.
*/
NETINFO_ITEM* FindNet( int aNetcode ) const;
/**
* Function FindNet overloaded
* searches for a net with the given name.
* @param aNetname A Netname to search for.
* @return NETINFO_ITEM* - the net or NULL if not found.
*/
NETINFO_ITEM* FindNet( const wxString& aNetname ) const;
/**
* Function FindModuleByReference
* searches for a MODULE within this board with the given
......@@ -787,7 +822,6 @@ public:
return m_TrackWidthList[m_TrackWidthSelector];
}
/**
* Function GetCurrentViaSize
* @return the current via size, according to the selected options
......@@ -799,7 +833,6 @@ public:
return m_ViasDimensionsList[m_ViaSizeSelector].m_Diameter;
}
/**
* Function GetCurrentViaDrill
* @return the current via size, according to the selected options
......@@ -837,7 +870,6 @@ public:
*/
bool Save( FILE* aFile ) const;
/**
* Function GetClass
* returns the class name.
......@@ -848,7 +880,6 @@ public:
return wxT( "BOARD" );
}
#if defined(DEBUG)
/**
......@@ -922,7 +953,6 @@ public:
return NULL;
}
/**
* Function GetAreaIndex
* returns the Area Index for the given Zone Container.
......@@ -940,7 +970,6 @@ public:
return -1;
}
/**
* Function GetAreaCount
* @return int - The number of Areas or ZONE_CONTAINER.
......@@ -950,7 +979,6 @@ public:
return (int) m_ZoneDescriptorList.size();
}
/* Functions used in test, merge and cut outlines */
/**
......@@ -1196,7 +1224,6 @@ public:
*/
void GetSortedPadListByXthenYCoord( std::vector<D_PAD*>& aVector );
/**
* Function GetTrace
* find the segment of \a aTrace at \a aPosition on \a aLayer if \a Layer is visible.
......
pcbnew/class_netclass.cpp
View file @ 4c2a1dd5
......@@ -195,7 +195,7 @@ void BOARD::SynchronizeNetsAndNetClasses()
// set all NETs to the default NETCLASS, then later override some
// as we go through the NETCLASSes.
int count = m_NetInfo->GetCount();
int count = m_NetInfo.GetNetCount();
for( int i=0; i<count; ++i )
{
NETINFO_ITEM* net = FindNet( i );
......
pcbnew/class_netinfo.h
View file @ 4c2a1dd5
......@@ -26,7 +26,6 @@ class BOARD;
class BOARD_ITEM;
/* Class RATSNEST_ITEM: describes a ratsnest line: a straight line connecting 2 pads */
/*****************************/
/* flags for a RATSNEST_ITEM */
......@@ -37,6 +36,11 @@ class BOARD_ITEM;
#define CH_ACTIF 8 /* Not routed. */
#define LOCAL_RATSNEST_ITEM 0x8000 /* Line between two pads of a single module. */
/**
* Class RATSNEST_ITEM
* describes a ratsnest line: a straight line connecting 2 pads
*/
class RATSNEST_ITEM
{
private:
......@@ -59,7 +63,6 @@ public:
return m_NetCode;
}
void SetNet( int aNetCode )
{
m_NetCode = aNetCode;
......@@ -87,37 +90,38 @@ public:
};
/***************************************************************/
/******************* class NETINFO *****************************/
/***************************************************************/
/**
* Class NETINFO
* is a container class for NETINFO_ITEM elements, which are the nets. That makes
* this class a container for the nets.
*/
class NETINFO_LIST
{
private:
BOARD* m_Parent;
std::vector<NETINFO_ITEM*> m_NetBuffer; // nets buffer list (name, design constraints ..
friend class BOARD;
public:
std::vector<D_PAD*> m_PadsFullList; // Entry for a sorted pad list (used in ratsnest
// calculations)
public: NETINFO_LIST( BOARD* aParent );
NETINFO_LIST( BOARD* aParent );
~NETINFO_LIST();
/**
* Function GetItem
* @param aNetcode = netcode to identify a given NETINFO_ITEM
* @return a NETINFO_ITEM pointer to the selected NETINFO_ITEM by its
* netcode, or NULL if not found
* @return NETINFO_ITEM* - by \a aNetcode, or NULL if not found
*/
NETINFO_ITEM* GetNetItem( int aNetcode );
NETINFO_ITEM* GetNetItem( int aNetcode ) const
{
if( unsigned( aNetcode ) >= GetNetCount() ) // catches < 0 too
return NULL;
return m_NetBuffer[aNetcode];
}
/**
* Function GetCount
* Function GetNetCount
* @return the number of nets ( always >= 1 )
* becuse the first net is the "not connected" net and always exists
* because the first net is the "not connected" net and always exists
*/
unsigned GetCount() { return m_NetBuffer.size(); }
unsigned GetNetCount() const { return m_NetBuffer.size(); }
/**
* Function Append
......@@ -126,33 +130,28 @@ public: NETINFO_LIST( BOARD* aParent );
void AppendNet( NETINFO_ITEM* aNewElement );
/**
* Function DeleteData
* delete the list of nets (and free memory)
*/
void DeleteData();
/**
* Function BuildListOfNets
* Build or rebuild the list of NETINFO_ITEM m_NetBuffer
* The list is sorted by names.
* Function GetPadCount
* @return the number of pads in board
*/
void BuildListOfNets();
unsigned GetPadCount() const { return m_PadsFullList.size(); }
/**
* Function GetPadsCount
* @return the number of pads in board
*/
unsigned GetPadsCount()
* Function GetPads
* returns a list of all the pads. The returned list is not
* sorted and contains pointers to PADS, but those pointers do not convey
* ownership of the respective PADs.
* @return std::vector<D_PAD*>& - a full list of pads
std::vector<D_PAD*>& GetPads()
{
return m_PadsFullList.size();
return m_PadsFullList;
}
*/
/**
* Function GetPad
* @return the pad idx from m_PadsFullList
*/
D_PAD* GetPad( unsigned aIdx )
D_PAD* GetPad( unsigned aIdx ) const
{
if( aIdx < m_PadsFullList.size() )
return m_PadsFullList[aIdx];
......@@ -160,19 +159,36 @@ public: NETINFO_LIST( BOARD* aParent );
return NULL;
}
private:
/**
* Function Build_Pads_Full_List
* Create the pad list
* initialise:
* Function DeleteData
* deletes the list of nets (and free memory)
*/
void clear();
/**
* Function BuildListOfNets
* builds or rebuilds the list of NETINFO_ITEMs
* The list is sorted by names.
*/
void buildListOfNets();
/**
* Function buildPadsFullList
* creates the pad list, and initializes:
* m_Pads (list of pads)
* set m_Status_Pcb = LISTE_PAD_OK;
* and clear for all pads in list the m_SubRatsnest member;
* clear m_Pcb->m_FullRatsnest
*/
void Build_Pads_Full_List();
void buildPadsFullList();
BOARD* m_Parent;
std::vector<NETINFO_ITEM*> m_NetBuffer; ///< net list (name, design constraints ..)
std::vector<D_PAD*> m_PadsFullList; ///< contains all pads, sorted by pad's netname.
///< can be used in ratsnest calculations.
};
......@@ -183,11 +199,11 @@ private:
class NETINFO_ITEM
{
private:
int m_NetCode; // this is a number equivalent to the net name
// Used for fast comparisons in ratsnest and DRC computations.
int m_NetCode; ///< A number equivalent to the net name.
///< Used for fast comparisons in ratsnest and DRC computations.
wxString m_Netname; // Full net name like /mysheet/mysubsheet/vout
// used by Eeschema
wxString m_Netname; ///< Full net name like /mysheet/mysubsheet/vout
///< used by Eeschema
wxString m_ShortNetname; // short net name, like vout from
// /mysheet/mysubsheet/vout
......@@ -233,13 +249,11 @@ public:
m_NetClassName = NETCLASS::Default;
}
NETCLASS* GetNetClass()
{
return m_NetClass;
}
/**
* Function GetClassName
* returns the class name
......@@ -249,7 +263,6 @@ public:
return m_NetClassName;
}
#if 1
/**
......@@ -272,7 +285,6 @@ public:
return m_NetClass->GetViaDiameter();
}
/**
* Function GetMicroViaSize
* returns the size of vias used to route this net
......@@ -283,7 +295,6 @@ public:
return m_NetClass->GetuViaDiameter();
}
/**
* Function GetViaDrillSize
* returns the size of via drills used to route this net
......@@ -294,7 +305,6 @@ public:
return m_NetClass->GetViaDrill();
}
/**
* Function GetViaDrillSize
* returns the size of via drills used to route this net
......@@ -318,7 +328,6 @@ public:
return m_NetClass->GetViaMinSize();
}
#endif
/**
......@@ -331,7 +340,6 @@ public:
return m_NetClass->GetClearance();
}
#endif
/* Reading and writing data on files */
......@@ -346,7 +354,6 @@ public:
*/
bool Save( FILE* aFile ) const;
/**
* Function Draw
* @todo we actually could show a NET, simply show all the tracks and
......@@ -354,7 +361,6 @@ public:
*/
void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, int aDrawMode, const wxPoint& offset );
/**
* Function GetNet
* @return int - the netcode
......@@ -383,14 +389,13 @@ public:
*/
void SetNetname( const wxString& aNetname );
/**
* Function DisplayInfo
* has knowledge about the frame and how and where to put status information
* about this object into the frame's message panel.
* Is virtual from EDA_ITEM.
* @param frame A EDA_DRAW_FRAME in which to print status information.
*/
/**
* Function DisplayInfo
* has knowledge about the frame and how and where to put status information
* about this object into the frame's message panel.
* Is virtual from EDA_ITEM.
* @param frame A EDA_DRAW_FRAME in which to print status information.
*/
void DisplayInfo( EDA_DRAW_FRAME* frame );
};
......
pcbnew/class_netinfo_item.cpp
View file @ 4c2a1dd5
......@@ -140,7 +140,6 @@ void NETINFO_ITEM::DisplayInfo( EDA_DRAW_FRAME* frame )
// Displays the net lenght of internal ICs connections (wires inside ICs):
txt = frame->CoordinateToString( lengthdie );
frame->AppendMsgPanel( _( "On Die" ), txt, RED );
}
......@@ -170,7 +169,9 @@ void RATSNEST_ITEM::Draw( EDA_DRAW_PANEL* panel,
const wxPoint& aOffset )
{
GRSetDrawMode( DC, aDrawMode );
int color = g_ColorsSettings.GetItemColor(RATSNEST_VISIBLE);
GRLine( &panel->m_ClipBox, DC, m_PadStart->m_Pos - aOffset,
m_PadEnd->m_Pos - aOffset, 0, color );
}
pcbnew/class_netinfolist.cpp
View file @ 4c2a1dd5
......@@ -23,31 +23,13 @@ NETINFO_LIST::NETINFO_LIST( BOARD* aParent )
NETINFO_LIST::~NETINFO_LIST()
{
DeleteData();
clear();
}
/**
* Function GetItem
* @param aNetcode = netcode to identify a given NETINFO_ITEM
* @return a NETINFO_ITEM pointer to the selected NETINFO_ITEM by its netcode, or NULL if not found
*/
NETINFO_ITEM* NETINFO_LIST::GetNetItem( int aNetcode )
void NETINFO_LIST::clear()
{
if( aNetcode < 0 || ( aNetcode > (int) ( GetCount() - 1 ) ) )
return NULL;
return m_NetBuffer[aNetcode];
}
/**
* Function DeleteData
* delete the list of nets (and free memory)
*/
void NETINFO_LIST::DeleteData()
{
for( unsigned ii = 0; ii < GetCount(); ii++ )
for( unsigned ii = 0; ii < GetNetCount(); ii++ )
delete m_NetBuffer[ii];
m_NetBuffer.clear();
......@@ -72,7 +54,7 @@ void NETINFO_LIST::AppendNet( NETINFO_ITEM* aNewElement )
* and expects to have a nets list sorted by an alphabetic case sensitive sort
*/
static bool PadlistSortByNetnames( const D_PAD* a, const D_PAD* b )
static bool padlistSortByNetnames( const D_PAD* a, const D_PAD* b )
{
return ( a->GetNetname().Cmp( b->GetNetname() ) ) < 0;
}
......@@ -90,23 +72,23 @@ static bool PadlistSortByNetnames( const D_PAD* a, const D_PAD* b )
* and expects to have a nets list sorted by an alphabetic case sensitive sort
* So do not change Build_Pads_Full_List() taht build a sorted list of pads
*/
void NETINFO_LIST::BuildListOfNets()
void NETINFO_LIST::buildListOfNets()
{
D_PAD* pad;
int nodes_count = 0;
NETINFO_ITEM* net_item;
D_PAD* pad;
int nodes_count = 0;
NETINFO_ITEM* net_item;
DeleteData(); // Remove all nets info and free memory
clear(); // Remove all nets info and free memory
// Create and add the "unconnected net", always existing,
// used to handle pads and tracks that are not member of a "real" net
net_item = new NETINFO_ITEM( (BOARD_ITEM*) m_Parent );
AppendNet( net_item );
/* Build the PAD list, sorted by net */
Build_Pads_Full_List();
// Build the PAD list, sorted by net
buildPadsFullList();
/* Build netnames list, and create a netcode for each netname */
// Build netnames list, and create a netcode for each netname
D_PAD* last_pad = NULL;
int netcode = 0;
......@@ -158,21 +140,20 @@ void NETINFO_LIST::BuildListOfNets()
}
/**
* Function Build_Pads_Full_List
* Create the pad list, sorted by net names (sorted by an alphabetic case sensitive sort)
* initialise:
* m_Pads (list of pads)
* set m_Status_Pcb = LISTE_PAD_OK;
* also clear m_Pcb->m_FullRatsnest that could have bad data
* (m_Pcb->m_FullRatsnest uses pointer to pads)
* Be aware NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname )
* when search a net by its net name does a binary search
* and expects to have a nets list sorted by an alphabetic case sensitive sort
* So do not change the sort function used here
*/
void NETINFO_LIST::Build_Pads_Full_List()
void NETINFO_LIST::buildPadsFullList()
{
/*
* initialize:
* m_Pads (list of pads)
* set m_Status_Pcb = LISTE_PAD_OK;
* also clear m_Pcb->m_FullRatsnest that could have bad data
* (m_Pcb->m_FullRatsnest uses pointer to pads)
* Be aware NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname )
* when search a net by its net name does a binary search
* and expects to have a nets list sorted by an alphabetic case sensitive sort
* So do not change the sort function used here
*/
if( m_Parent->m_Status_Pcb & LISTE_PAD_OK )
return;
......@@ -180,7 +161,7 @@ void NETINFO_LIST::Build_Pads_Full_List()
m_PadsFullList.clear();
m_Parent->m_FullRatsnest.clear();
/* Clear variables used in rastnest computation */
// Clear variables used in ratsnest computation
for( MODULE* module = m_Parent->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->m_Pads; pad; pad = pad->Next() )
......@@ -193,8 +174,7 @@ void NETINFO_LIST::Build_Pads_Full_List()
}
// Sort pad list per net
//
sort( m_PadsFullList.begin(), m_PadsFullList.end(), PadlistSortByNetnames );
sort( m_PadsFullList.begin(), m_PadsFullList.end(), padlistSortByNetnames );
m_Parent->m_Status_Pcb = LISTE_PAD_OK;
}
pcbnew/clean.cpp
View file @ 4c2a1dd5
......@@ -69,7 +69,7 @@ void CleanupTracks( PCB_EDIT_FRAME* aFrame,
/* Rebuild the pad infos (pad list and netcodes) to ensure an up to date info */
aFrame->GetBoard()->m_Status_Pcb = 0;
aFrame->GetBoard()->m_NetInfo->BuildListOfNets();
aFrame->GetBoard()->BuildListOfNets();
if( aCleanVias ) // delete redundant vias
{
......
pcbnew/connect.cpp
View file @ 4c2a1dd5
......@@ -677,9 +677,9 @@ void CONNECTIONS::Propagate_SubNets()
void PCB_BASE_FRAME::TestConnections()
{
// Clear the cluster identifier for all pads
for( unsigned i = 0; i< m_Pcb->GetPadsCount(); ++i )
for( unsigned i = 0; i< m_Pcb->GetPadCount(); ++i )
{
D_PAD* pad = m_Pcb->m_NetInfo->GetPad(i);
D_PAD* pad = m_Pcb->GetPad(i);
pad->SetZoneSubNet( 0 );
pad->SetSubNet( 0 );
......@@ -720,9 +720,9 @@ void PCB_BASE_FRAME::TestNetConnection( wxDC* aDC, int aNetCode )
Compile_Ratsnest( aDC, true );
// Clear the cluster identifier (subnet) of pads for this net
for( unsigned i = 0; i < m_Pcb->GetPadsCount(); ++i )
for( unsigned i = 0; i < m_Pcb->GetPadCount(); ++i )
{
D_PAD* pad = m_Pcb->m_NetInfo->GetPad(i);
D_PAD* pad = m_Pcb->GetPad(i);
int pad_net_code = pad->GetNet();
if( pad_net_code < aNetCode )
......@@ -786,7 +786,8 @@ void PCB_BASE_FRAME::RecalculateAllTracksNetcode()
TRACK* curr_track;
// Build the net info list
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->BuildListOfNets();
// Reset variables and flags used in computation
curr_track = m_Pcb->m_Track;
for( ; curr_track != NULL; curr_track = curr_track->Next() )
......@@ -801,7 +802,7 @@ void PCB_BASE_FRAME::RecalculateAllTracksNetcode()
}
// If no pad, reset pointers and netcode, and do nothing else
if( m_Pcb->GetPadsCount() == 0 )
if( m_Pcb->GetPadCount() == 0 )
return;
CONNECTIONS connections( m_Pcb );
......
pcbnew/drc_clearance_test_functions.cpp
View file @ 4c2a1dd5
......@@ -276,9 +276,9 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
// Compute the min distance to pads
if( testPads )
{
for( unsigned ii = 0; ii<m_pcb->GetPadsCount(); ++ii )
for( unsigned ii = 0; ii<m_pcb->GetPadCount(); ++ii )
{
D_PAD* pad = m_pcb->m_NetInfo->GetPad( ii );
D_PAD* pad = m_pcb->GetPad( ii );
/* No problem if pads are on an other layer,
* But if a drill hole exists (a pad on a single layer can have a hole!)
......
pcbnew/export_gencad.cpp
View file @ 4c2a1dd5
......@@ -262,12 +262,10 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb )
fputs( "$PADS\n", aFile );
// Enumerate and sort the pads
if( aPcb->GetPadsCount() > 0 )
if( aPcb->GetPadCount() > 0 )
{
pads.insert( pads.end(),
aPcb->m_NetInfo->m_PadsFullList.begin(),
aPcb->m_NetInfo->m_PadsFullList.end() );
qsort( &pads[0], aPcb->GetPadsCount(), sizeof( D_PAD* ),
pads = aPcb->GetPads();
qsort( &pads[0], aPcb->GetPadCount(), sizeof( D_PAD* ),
PadListSortByShape );
}
......@@ -643,9 +641,9 @@ static void CreateSignalsSection( FILE* aFile, BOARD* aPcb )
fputs( "$SIGNALS\n", aFile );
for( unsigned ii = 0; ii < aPcb->m_NetInfo->GetCount(); ii++ )
for( unsigned ii = 0; ii < aPcb->GetNetCount(); ii++ )
{
net = aPcb->m_NetInfo->GetNetItem( ii );
net = aPcb->FindNet( ii );
if( net->GetNetname() == wxEmptyString ) // dummy netlist (no connection)
{
......
pcbnew/highlight.cpp
View file @ 4c2a1dd5
......@@ -63,9 +63,9 @@ void PCB_EDIT_FRAME::ListNetsAndSelect( wxCommandEvent& event )
return;
wxString Line;
for( unsigned ii = 0; ii < GetBoard()->m_NetInfo->GetCount(); ii++ )
for( unsigned ii = 0; ii < GetBoard()->GetNetCount(); ii++ )
{
net = GetBoard()->m_NetInfo->GetNetItem( ii );
net = GetBoard()->m_NetInfo.GetNetItem( ii );
if( !WildCompareString( netFilter, net->GetNetname(), false ) )
continue;
......@@ -84,9 +84,9 @@ void PCB_EDIT_FRAME::ListNetsAndSelect( wxCommandEvent& event )
unsigned netcode = (unsigned) choiceDlg.GetSelection();
// Search for the net selected.
for( unsigned ii = 0; ii < GetBoard()->m_NetInfo->GetCount(); ii++ )
for( unsigned ii = 0; ii < GetBoard()->GetNetCount(); ii++ )
{
net = GetBoard()->m_NetInfo->GetNetItem( ii );
net = GetBoard()->FindNet( ii );
if( !WildCompareString( netFilter, net->GetNetname(), false ) )
continue;
......
pcbnew/ioascii.cpp
View file @ 4c2a1dd5
......@@ -824,7 +824,7 @@ bool PCB_EDIT_FRAME::WriteGeneralDescrPcb( FILE* File )
fprintf( File, "Nzone %d\n", GetBoard()->GetNumSegmZone() );
fprintf( File, "BoardThickness %d\n", GetBoard()->GetDesignSettings().m_BoardThickness );
fprintf( File, "Nmodule %d\n", NbModules );
fprintf( File, "Nnets %d\n", GetBoard()->m_NetInfo->GetCount() );
fprintf( File, "Nnets %d\n", GetBoard()->GetNetCount() );
fprintf( File, "$EndGENERAL\n\n" );
return true;
}
......@@ -1010,7 +1010,7 @@ int PCB_EDIT_FRAME::ReadPcbFile( LINE_READER* aReader, bool Append )
if( TESTLINE( "EQUIPOT" ) )
{
NETINFO_ITEM* net = new NETINFO_ITEM( board );
board->m_NetInfo->AppendNet( net );
board->m_NetInfo.AppendNet( net );
net->ReadDescr( aReader );
continue;
}
......@@ -1133,7 +1133,7 @@ int PCB_EDIT_FRAME::ReadPcbFile( LINE_READER* aReader, bool Append )
GetBoard()->m_Status_Pcb = 0;
// Build the net info list
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->m_NetInfo.BuildListOfNets();
board->SynchronizeNetsAndNetClasses();
......
pcbnew/item_io.cpp
View file @ 4c2a1dd5
......@@ -41,7 +41,6 @@
#include "pcbnew.h"
#include "pcbnew_id.h"
#include "autorout.h"
#include "pcb_plot_params.h"
#include "3d_struct.h"
#include "trigo.h"
......@@ -60,8 +59,8 @@ bool BOARD::Save( FILE* aFile ) const
BOARD_ITEM* item;
// save the nets
for( unsigned ii = 0; ii < m_NetInfo->GetCount(); ii++ )
if( !m_NetInfo->GetNetItem( ii )->Save( aFile ) )
for( unsigned ii = 0; ii < GetNetCount(); ii++ )
if( !FindNet( ii )->Save( aFile ) )
goto out;
// Saved nets do not include netclass names, so save netclasses after nets.
......
pcbnew/kicad_plugin.cpp
View file @ 4c2a1dd5
This diff is collapsed.
pcbnew/kicad_plugin.h
View file @ 4c2a1dd5
......@@ -40,6 +40,9 @@ class ZONE_CONTAINER;
class DIMENSION;
class NETINFO_ITEM;
class TEXTE_MODULE;
class EDGE_MODULE;
class TRACK;
class SEGZONE;
/**
......@@ -73,6 +76,7 @@ protected:
LINE_READER* m_reader; ///< no ownership here.
FILE* m_fp; ///< no ownership here.
wxString m_filename; ///< for saves only, name is in m_reader for loads
wxString m_field; ///< reused to stuff MODULE fields.
......@@ -88,9 +92,6 @@ protected:
double biuToDisk; ///< convert from BIUs to disk engineering units with this scale factor
double diskToBiu; ///< convert from disk engineering units to BIUs with this scale factor
/// convert a BIU to engineering units by scaling and formatting to ASCII.
std::string biuFmt( BIU aValue );
/**
* Function biuParse
* parses an ASCII decimal floating point value and scales it into a BIU
......@@ -133,12 +134,12 @@ protected:
void loadMODULE();
void load3D( MODULE* aModule );
void loadPAD( MODULE* aModule );
void loadTEXTE_MODULE( TEXTE_MODULE* aText );
void loadMODULE_TEXT( TEXTE_MODULE* aText );
void loadEDGE_MODULE( MODULE* aModule );
void loadDRAWSEGMENT();
void loadNETINFO_ITEM();
void loadPCB_TEXTE();
void loadPCB_TEXT();
void loadNETCLASS();
/**
......@@ -158,6 +159,50 @@ protected:
void loadPCB_TARGET(); // "$PCB_TARGET"
//-----</ load/parse functions>---------------------------------------------
//-----<save functions>-----------------------------------------------------
/**
* Function checkWriteError
* checks to see if there is an error on the output FILE, and its ability to
* continue saving to disk.
*/
void checkWriteError( const char* aCaller ) const;
/// convert a BIU to engineering units by scaling and formatting to ASCII.
std::string biuFmt( BIU aValue );
void saveAllSections() const;
void saveGENERAL() const;
void saveSHEET() const;
void saveSETUP() const;
void saveBOARD() const;
void saveMODULE( const MODULE* aModule ) const;
void saveNETINFO_ITEM( const NETINFO_ITEM* aNet ) const;
void saveNETCLASSES() const;
void saveNETCLASS( const NETCLASS* aNetclass ) const;
void savePCB_TEXT( const TEXTE_PCB* aText ) const;
void saveEDGE_MODULE( const EDGE_MODULE* aEdge ) const;
void saveTARGET( const PCB_TARGET* aTarget ) const;
void saveDIMENTION( const DIMENSION* aDimension ) const;
void saveTRACK( const TRACK* aTrack ) const;
/**
* Function saveSEGZONE
* saves the oldschool zones, now outdated in favor of polygon zones.
*/
void saveSEGZONE( const SEGZONE* aZone ) const;
/**
* Function saveZONE_CONTAINER
* saves the new polygon zones.
*/
void saveZONE_CONTAINER( const ZONE_CONTAINER* aZone ) const;
//-----</save functions>----------------------------------------------------
};
#endif // KICAD_PLUGIN_H_
pcbnew/librairi.cpp
View file @ 4c2a1dd5
......@@ -134,7 +134,7 @@ MODULE* FOOTPRINT_EDIT_FRAME::Import_Module()
module->DisplayInfo( this );
PlaceModule( module, NULL );
GetBoard()->m_Status_Pcb = 0;
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->BuildListOfNets();
return module;
}
......
pcbnew/loadcmp.cpp
View file @ 4c2a1dd5
......@@ -86,7 +86,7 @@ bool FOOTPRINT_EDIT_FRAME::Load_Module_From_BOARD( MODULE* aModule )
aModule->m_Flags = 0;
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->BuildListOfNets();
GetScreen()->SetCrossHairPosition( wxPoint( 0, 0 ) );
PlaceModule( aModule, NULL );
......@@ -196,7 +196,7 @@ MODULE* PCB_BASE_FRAME::Load_Module_From_Library( const wxString& library, wxDC*
*/
// GetBoard()->m_Pcb->m_NetInfo->BuildListOfNets();
// GetBoard()->m_Pcb->m_NetInfo.BuildListOfNets();
RecalculateAllTracksNetcode();
if( DC )
......
pcbnew/modedit.cpp
View file @ 4c2a1dd5
......@@ -242,7 +242,7 @@ void FOOTPRINT_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event )
// Initialize data relative to nets and netclasses (for a new
// module the defaults are used)
// This is mandatory to handle and draw pads
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->BuildListOfNets();
redraw = true;
module->SetPosition( wxPoint( 0, 0 ) );
......
pcbnew/modules.cpp
View file @ 4c2a1dd5
......@@ -170,7 +170,7 @@ void Abort_MoveOrCopyModule( EDA_DRAW_PANEL* Panel, wxDC* DC )
module->DeleteStructure();
module = NULL;
pcbframe->GetBoard()->m_Status_Pcb = 0;
pcbframe->GetBoard()->m_NetInfo->BuildListOfNets();
pcbframe->GetBoard()->BuildListOfNets();
}
}
......
pcbnew/ratsnest.cpp
View file @ 4c2a1dd5
......@@ -135,7 +135,7 @@ void PCB_BASE_FRAME::Compile_Ratsnest( wxDC* aDC, bool aDisplayStatus )
{
wxString msg;
GetBoard()->m_Status_Pcb = 0; /* we want a full ratsnest computation, from the scratch */
GetBoard()->m_Status_Pcb = 0; // we want a full ratsnest computation, from the scratch
ClearMsgPanel();
// Rebuild the full pads and net info list
......@@ -143,9 +143,9 @@ void PCB_BASE_FRAME::Compile_Ratsnest( wxDC* aDC, bool aDisplayStatus )
if( aDisplayStatus )
{
msg.Printf( wxT( " %d" ), m_Pcb->GetPadsCount() );
msg.Printf( wxT( " %d" ), m_Pcb->GetPadCount() );
AppendMsgPanel( wxT( "Pads" ), msg, RED );
msg.Printf( wxT( " %d" ), m_Pcb->m_NetInfo->GetCount() );
msg.Printf( wxT( " %d" ), m_Pcb->GetNetCount() );
AppendMsgPanel( wxT( "Nets" ), msg, CYAN );
}
......@@ -158,7 +158,7 @@ void PCB_BASE_FRAME::Compile_Ratsnest( wxDC* aDC, bool aDisplayStatus )
*/
Build_Board_Ratsnest();
/* Compute the pad connections due to the existing tracks (physical connections) */
// Compute the pad connections due to the existing tracks (physical connections)
TestConnections();
/* Compute the active ratsnest, i.e. the unconnected links
......@@ -206,16 +206,16 @@ void PCB_BASE_FRAME::Build_Board_Ratsnest()
m_Pcb->m_FullRatsnest.clear();
if( m_Pcb->GetPadsCount() == 0 )
if( m_Pcb->GetPadCount() == 0 )
return;
/* Created pad list and the net_codes if needed */
if( (m_Pcb->m_Status_Pcb & NET_CODES_OK) == 0 )
m_Pcb->m_NetInfo->BuildListOfNets();
m_Pcb->BuildListOfNets();
for( unsigned ii = 0; ii<m_Pcb->GetPadsCount(); ++ii )
for( unsigned ii = 0; ii<m_Pcb->GetPadCount(); ++ii )
{
pad = m_Pcb->m_NetInfo->GetPad( ii );
pad = m_Pcb->GetPad( ii );
pad->SetSubRatsnest( 0 );
}
......@@ -227,7 +227,7 @@ void PCB_BASE_FRAME::Build_Board_Ratsnest()
// (net_code = 0 -> no connect)
noconn = 0;
MIN_SPAN_TREE_PADS min_spanning_tree;
for( ; current_net_code < m_Pcb->m_NetInfo->GetCount(); current_net_code++ )
for( ; current_net_code < m_Pcb->GetNetCount(); current_net_code++ )
{
NETINFO_ITEM* net = m_Pcb->FindNet( current_net_code );
......@@ -439,13 +439,13 @@ void PCB_BASE_FRAME::TestForActiveLinksInRatsnest( int aNetCode )
D_PAD* pad;
NETINFO_ITEM* net;
if( m_Pcb->GetPadsCount() == 0 )
if( m_Pcb->GetPadCount() == 0 )
return;
if( (m_Pcb->m_Status_Pcb & LISTE_RATSNEST_ITEM_OK) == 0 )
Build_Board_Ratsnest();
for( int net_code = 1; net_code < (int) m_Pcb->m_NetInfo->GetCount(); net_code++ )
for( int net_code = 1; net_code < (int) m_Pcb->GetNetCount(); net_code++ )
{
net = m_Pcb->FindNet( net_code );
......@@ -514,7 +514,7 @@ void PCB_BASE_FRAME::build_ratsnest_module( MODULE* aModule )
if( (GetBoard()->m_Status_Pcb & LISTE_PAD_OK) == 0 )
{
GetBoard()->m_Status_Pcb = 0;
GetBoard()->m_NetInfo->BuildListOfNets();
GetBoard()->BuildListOfNets();
}
/* Compute the "local" ratsnest if needed (when this footprint starts move)
......
pcbnew/solve.cpp
View file @ 4c2a1dd5
......@@ -508,12 +508,11 @@ static int Autoroute_One_Track( PCB_EDIT_FRAME* pcbframe,
/* Regenerates the remaining barriers (which may encroach on the placement bits precedent)
*/
i = pcbframe->GetBoard()->GetPadsCount();
i = pcbframe->GetBoard()->GetPadCount();
for( unsigned ii = 0; ii < pcbframe->GetBoard()->GetPadsCount(); ii++ )
for( unsigned ii = 0; ii < pcbframe->GetBoard()->GetPadCount(); ii++ )
{
D_PAD* ptr = pcbframe->GetBoard()->m_NetInfo->GetPad( ii );
D_PAD* ptr = pcbframe->GetBoard()->GetPad( ii );
if( ( pt_cur_ch->m_PadStart != ptr ) && ( pt_cur_ch->m_PadEnd != ptr ) )
{
......
pcbnew/specctra_export.cpp
View file @ 4c2a1dd5
......@@ -1172,7 +1172,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR )
std::string componentId;
// find the highest numbered netCode within the board.
int highestNetCode = aBoard->m_NetInfo->GetCount() - 1;
int highestNetCode = aBoard->GetNetCount() - 1;
deleteNETs();
// expand the net vector to highestNetCode+1, setting empty to NULL
......@@ -1182,9 +1182,9 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR )
for( unsigned i=1; i<nets.size(); ++i )
nets[i] = new NET( pcb->network );
for( unsigned ii = 0; ii < aBoard->m_NetInfo->GetCount(); ii++ )
for( unsigned ii = 0; ii < aBoard->GetNetCount(); ii++ )
{
NETINFO_ITEM* net = aBoard->m_NetInfo->GetNetItem(ii);
NETINFO_ITEM* net = aBoard->FindNet(ii);
int netcode = net->GetNet();
if( netcode > 0 )
nets[ netcode ]->net_id = TO_UTF8( net->GetNetname() );
......
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