Loading change_log.txt +8 −1 Original line number Diff line number Diff line Loading @@ -4,6 +4,14 @@ Started 2007-June-11 Please add newer entries at the top, list the date and your name with email address. 2007-Oct-17 UPDATE Geoff Harland <gharlandau@yahoo.com.au> ================================================================================ + pcbnew * Rolled back previous changes (made in revision 336) that edited the values of vias' Shape property (following feedback from Jean-Pierre Charras concerning the true significance of that property). 2007-Oct-13 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr> ================================================================================ + pcbnew: Loading @@ -22,7 +30,6 @@ email address. enhancements in connectivity computation 2007-Oct-15 UPDATE Geoff Harland <gharlandau@yahoo.com.au> ================================================================================ + pcbnew Loading pcbnew/class_track.cpp +7 −50 Original line number Diff line number Diff line Loading @@ -226,6 +226,7 @@ bool SEGVIA::IsOnLayer( int layer_number ) const // VIA_BORGNE ou VIA_ENTERREE: */ int bottom_layer, top_layer; ReturnLayerPair( &top_layer, &bottom_layer ); Loading Loading @@ -547,7 +548,6 @@ bool TRACK::WriteTrackDescr( FILE* File ) /********************************************/ { int type = 0; int shape; // Stores genuine value of via's shape property if( Type() == TYPEVIA ) type = 1; Loading @@ -555,50 +555,7 @@ bool TRACK::WriteTrackDescr( FILE* File ) if( GetState( DELETED ) ) return FALSE; // In the case of a via, check the values of its top_layer and // bottom_layer properties, to determine what value should *really* // be assigned to its shape property (as all versions of KiCad up // until revision 335 (committed on 2007-Oct-13) could sometimes // assign an inappropriate value to that property). if( Type() == TYPEVIA ) { // int bottom_layer, top_layer; // ((SEGVIA*)this)->ReturnLayerPair( &top_layer, &bottom_layer ); // For reasons of efficiency, replace the previous two commands // with these (next three) commands. int bottom_layer = (m_Layer >> 4) & 15; int top_layer = m_Layer & 15; if( bottom_layer > top_layer ) EXCHG( bottom_layer, top_layer ); // Now determine what type of via this really is if( bottom_layer == COPPER_LAYER_N && top_layer == CMP_N ) { // The via is really of a "standard" (through-hole) type shape = VIA_NORMALE; } else if( bottom_layer == COPPER_LAYER_N || top_layer == CMP_N ) { // The via is really of a "blind" type shape = VIA_BORGNE; } else { // The via is really of a "buried" type shape = VIA_ENTERREE; } } else shape = m_Shape; // Cater for other (non-via) types of objects // fprintf( File, "Po %d %d %d %d %d %d %d\n", m_Shape, // m_Start.x, m_Start.y, m_End.x, m_End.y, m_Width, m_Drill ); // (Replace m_Shape within the previous command with shape) fprintf( File, "Po %d %d %d %d %d %d %d\n", shape, fprintf( File, "Po %d %d %d %d %d %d %d\n", m_Shape, m_Start.x, m_Start.y, m_End.x, m_End.y, m_Width, m_Drill ); fprintf( File, "De %d %d %d %lX %X\n", Loading @@ -609,7 +566,7 @@ bool TRACK::WriteTrackDescr( FILE* File ) } /**********************************************************************/ /*********************************************************************/ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) /*********************************************************************/ Loading pcbnew/editrack-part2.cpp +18 −50 Original line number Diff line number Diff line Loading @@ -214,9 +214,13 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) DrawPanel->ManageCurseur( DrawPanel, DC, FALSE ); // Create the via - but before doing so, determine what // value should really be assigned to its Shape property. // (Use ii to temporarily "store" the appropriate value.) /* create the via */ Via = new SEGVIA( m_Pcb ); Via->m_Flags = IS_NEW; Via->m_Width = g_DesignSettings.m_CurrentViaSize; Via->m_Shape = g_DesignSettings.m_CurrentViaType; Via->SetNet( g_HightLigth_NetCode ); Via->m_Start = Via->m_End = g_CurrentTrackSegment->m_End; int old_layer = GetScreen()->m_Active_Layer; Loading @@ -226,59 +230,23 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) else GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM; /* Assess the type of via */ if( g_DesignSettings.m_CurrentViaType == VIA_NORMALE ) // normal via { ii = VIA_NORMALE; } else // Either a blind via or buried via was "requested", but still // check both layers of the layer pair, to determine the truly // appropriate value to assign to the via's Type property. { if( ( old_layer == COPPER_LAYER_N && GetScreen()->m_Active_Layer == CMP_N ) || ( old_layer == CMP_N && GetScreen()->m_Active_Layer == COPPER_LAYER_N ) ) { // Specify the via's Shape property as Standard ii = VIA_NORMALE; } else if( old_layer == COPPER_LAYER_N || old_layer == CMP_N || GetScreen()->m_Active_Layer == COPPER_LAYER_N || GetScreen()->m_Active_Layer == CMP_N ) /* Adjust the via layer pair */ if( Via->Shape() == VIA_ENTERREE ) { // Specify the via's Shape property as Blind ii = VIA_BORGNE; Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); } else else if( Via->Shape() == VIA_BORGNE ) //blind via { // Specify the via's Shape property as Buried ii = VIA_ENTERREE; } // A revoir! ( la via devrait deboucher sur 1 cote ) Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); } Via = new SEGVIA( m_Pcb ); Via->m_Flags = IS_NEW; Via->m_Width = g_DesignSettings.m_CurrentViaSize; Via->m_Shape = ii; // ( instead of g_DesignSettings.m_CurrentViaType ) Via->SetNet( g_HightLigth_NetCode ); Via->m_Start = Via->m_End = g_CurrentTrackSegment->m_End; /* Adjust the via layer pair */ if( Via->Shape() == VIA_NORMALE ) // Normal via else { // Usual via is from copper to component; layer pair is 0 and 0x0F. Via->SetLayerPair( COPPER_LAYER_N, LAYER_CMP_N ); } else // Either a blind via or buried via. { if( old_layer < GetScreen()->m_Active_Layer) Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); else Via->SetLayerPair( GetScreen()->m_Active_Layer, old_layer ); } if( Drc_On &&( Drc( this, DC, Via, m_Pcb->m_Track, 1 ) == BAD_DRC ) ) { Loading Loading
change_log.txt +8 −1 Original line number Diff line number Diff line Loading @@ -4,6 +4,14 @@ Started 2007-June-11 Please add newer entries at the top, list the date and your name with email address. 2007-Oct-17 UPDATE Geoff Harland <gharlandau@yahoo.com.au> ================================================================================ + pcbnew * Rolled back previous changes (made in revision 336) that edited the values of vias' Shape property (following feedback from Jean-Pierre Charras concerning the true significance of that property). 2007-Oct-13 UPDATE Jean-Pierre Charras <jean-pierre.charras@inpg.fr> ================================================================================ + pcbnew: Loading @@ -22,7 +30,6 @@ email address. enhancements in connectivity computation 2007-Oct-15 UPDATE Geoff Harland <gharlandau@yahoo.com.au> ================================================================================ + pcbnew Loading
pcbnew/class_track.cpp +7 −50 Original line number Diff line number Diff line Loading @@ -226,6 +226,7 @@ bool SEGVIA::IsOnLayer( int layer_number ) const // VIA_BORGNE ou VIA_ENTERREE: */ int bottom_layer, top_layer; ReturnLayerPair( &top_layer, &bottom_layer ); Loading Loading @@ -547,7 +548,6 @@ bool TRACK::WriteTrackDescr( FILE* File ) /********************************************/ { int type = 0; int shape; // Stores genuine value of via's shape property if( Type() == TYPEVIA ) type = 1; Loading @@ -555,50 +555,7 @@ bool TRACK::WriteTrackDescr( FILE* File ) if( GetState( DELETED ) ) return FALSE; // In the case of a via, check the values of its top_layer and // bottom_layer properties, to determine what value should *really* // be assigned to its shape property (as all versions of KiCad up // until revision 335 (committed on 2007-Oct-13) could sometimes // assign an inappropriate value to that property). if( Type() == TYPEVIA ) { // int bottom_layer, top_layer; // ((SEGVIA*)this)->ReturnLayerPair( &top_layer, &bottom_layer ); // For reasons of efficiency, replace the previous two commands // with these (next three) commands. int bottom_layer = (m_Layer >> 4) & 15; int top_layer = m_Layer & 15; if( bottom_layer > top_layer ) EXCHG( bottom_layer, top_layer ); // Now determine what type of via this really is if( bottom_layer == COPPER_LAYER_N && top_layer == CMP_N ) { // The via is really of a "standard" (through-hole) type shape = VIA_NORMALE; } else if( bottom_layer == COPPER_LAYER_N || top_layer == CMP_N ) { // The via is really of a "blind" type shape = VIA_BORGNE; } else { // The via is really of a "buried" type shape = VIA_ENTERREE; } } else shape = m_Shape; // Cater for other (non-via) types of objects // fprintf( File, "Po %d %d %d %d %d %d %d\n", m_Shape, // m_Start.x, m_Start.y, m_End.x, m_End.y, m_Width, m_Drill ); // (Replace m_Shape within the previous command with shape) fprintf( File, "Po %d %d %d %d %d %d %d\n", shape, fprintf( File, "Po %d %d %d %d %d %d %d\n", m_Shape, m_Start.x, m_Start.y, m_End.x, m_End.y, m_Width, m_Drill ); fprintf( File, "De %d %d %d %lX %X\n", Loading @@ -609,7 +566,7 @@ bool TRACK::WriteTrackDescr( FILE* File ) } /**********************************************************************/ /*********************************************************************/ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) /*********************************************************************/ Loading
pcbnew/editrack-part2.cpp +18 −50 Original line number Diff line number Diff line Loading @@ -214,9 +214,13 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) DrawPanel->ManageCurseur( DrawPanel, DC, FALSE ); // Create the via - but before doing so, determine what // value should really be assigned to its Shape property. // (Use ii to temporarily "store" the appropriate value.) /* create the via */ Via = new SEGVIA( m_Pcb ); Via->m_Flags = IS_NEW; Via->m_Width = g_DesignSettings.m_CurrentViaSize; Via->m_Shape = g_DesignSettings.m_CurrentViaType; Via->SetNet( g_HightLigth_NetCode ); Via->m_Start = Via->m_End = g_CurrentTrackSegment->m_End; int old_layer = GetScreen()->m_Active_Layer; Loading @@ -226,59 +230,23 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) else GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM; /* Assess the type of via */ if( g_DesignSettings.m_CurrentViaType == VIA_NORMALE ) // normal via { ii = VIA_NORMALE; } else // Either a blind via or buried via was "requested", but still // check both layers of the layer pair, to determine the truly // appropriate value to assign to the via's Type property. { if( ( old_layer == COPPER_LAYER_N && GetScreen()->m_Active_Layer == CMP_N ) || ( old_layer == CMP_N && GetScreen()->m_Active_Layer == COPPER_LAYER_N ) ) { // Specify the via's Shape property as Standard ii = VIA_NORMALE; } else if( old_layer == COPPER_LAYER_N || old_layer == CMP_N || GetScreen()->m_Active_Layer == COPPER_LAYER_N || GetScreen()->m_Active_Layer == CMP_N ) /* Adjust the via layer pair */ if( Via->Shape() == VIA_ENTERREE ) { // Specify the via's Shape property as Blind ii = VIA_BORGNE; Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); } else else if( Via->Shape() == VIA_BORGNE ) //blind via { // Specify the via's Shape property as Buried ii = VIA_ENTERREE; } // A revoir! ( la via devrait deboucher sur 1 cote ) Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); } Via = new SEGVIA( m_Pcb ); Via->m_Flags = IS_NEW; Via->m_Width = g_DesignSettings.m_CurrentViaSize; Via->m_Shape = ii; // ( instead of g_DesignSettings.m_CurrentViaType ) Via->SetNet( g_HightLigth_NetCode ); Via->m_Start = Via->m_End = g_CurrentTrackSegment->m_End; /* Adjust the via layer pair */ if( Via->Shape() == VIA_NORMALE ) // Normal via else { // Usual via is from copper to component; layer pair is 0 and 0x0F. Via->SetLayerPair( COPPER_LAYER_N, LAYER_CMP_N ); } else // Either a blind via or buried via. { if( old_layer < GetScreen()->m_Active_Layer) Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); else Via->SetLayerPair( GetScreen()->m_Active_Layer, old_layer ); } if( Drc_On &&( Drc( this, DC, Via, m_Pcb->m_Track, 1 ) == BAD_DRC ) ) { Loading