bug fix - dirty debug for 393 broke microzed (hardwired UART0)

ezynq_uboot.py

@@ -720,26 +720,9 @@ int arch_cpu_init(void)
 '''
 
         if ('uart_xmit' in self.sections) and self.features.get_par_value_or_none('LAST_PRINT_DEBUG'):
-            self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
-            self.cfile+='\tuart_putc(0xd);\n'
-            self.cfile+='\tuart_putc(0xa);\n'
-            self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
-            self.cfile+='\tuart_putc(0xd);\n'
-            self.cfile+='\tuart_putc(0xa);\n'
-#            self.cfile+='\twhile((readl(0xe000002c) & 0x808) != 8); /* uart0.channel_sts  Channel status */\n'
-            self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
-            self.cfile+='\tuart_putc(0xd);\n'
-            self.cfile+='\tuart_putc(0xa);\n'
-            self.cfile+='\tuart_put_hex(readl(0xe000002c));\n'
-            self.cfile+='\tuart_putc(0xd);\n'
-            self.cfile+='\tuart_putc(0xa);\n'
-            self.cfile+='\tuart_put_hex(0x12345678);\n'
-            self.cfile+='\tuart_putc(0xd);\n'
-            self.cfile+='\tuart_putc(0xa);\n'
             self.cfile+='\tuart_put_hex(0x12345678);\n'
             self.cfile+='\tuart_putc(0xd);\n'
             self.cfile+='\tuart_putc(0xa);\n'
-            self.cfile+='\twhile((readl(0xe000002c) & 0x808) != 8); /* uart0.channel_sts  Channel status */\n'
         if 'uart_xmit' in self.sections:
             self.cfile+='\tuart_wait_tx_fifo_empty(); /* u-boot may re-program UART differently, wait all is sent before getting there */\n'
 #uart_wait_tx_fifo_empty() - add if u-boot debug is on

u-boot-tree/include/configs/ezynq/zed_ezynq.h

@@ -30,7 +30,7 @@
 #define CONFIG_EZYNQ_BOOT_DEBUG        Y   /* configure UARTx and send register dumps there.*/
 #define CONFIG_EZYNQ_LOCK_SLCR         OFF /* Lock SLCR registers when all is done. */
 #define CONFIG_EZYNQ_LED_DEBUG          47 /* toggle LED during boot */
-#define CONFIG_EZYNQ_UART_DEBUG_USE_LED    /* turn on/off LED while waiting for transmit FIFO not full */
+#define CONFIG_EZYNQ_UART_DEBUG_USE_LED N  /* turn on/off LED while waiting for transmit FIFO not full */
 
 #define CONFIG_EZYNQ_DUMP_SLCR_EARLY     N /* Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
 #define CONFIG_EZYNQ_DUMP_DDRC_EARLY     N /* Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
@@ -38,29 +38,29 @@
 #define CONFIG_EZYNQ_DUMP_DDRC_LATE      N  /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
 #define CONFIG_EZYNQ_DUMP_TRAINING_EARLY N /* Training results registers before DDRC initialization */
 #define CONFIG_EZYNQ_DUMP_TRAINING_LATE  Y /* Training results registers after DDRC initialization */
-#define CONFIG_EZYNQ_DUMP_OCM            y /* Dump (some of) OCM data */
-#define CONFIG_EZYNQ_DUMP_DDR            y  /* Dump (some of) DDR data */
+#define CONFIG_EZYNQ_DUMP_OCM            n /* Dump (some of) OCM data */
+#define CONFIG_EZYNQ_DUMP_DDR            n  /* Dump (some of) DDR data */
 #if 1
 #define CONFIG_EZYNQ_DUMP_OCM_LOW        0x0   /* OCM dump start (deafault 0)     */
-#define CONFIG_EZYNQ_DUMP_OCM_HIGH     0x2ff   /* OCM dump end   (deafault 0x2ff, full - 0x2ffff) */
+#define CONFIG_EZYNQ_DUMP_OCM_HIGH   0x2ffff   /* OCM dump end   (deafault 0x2ff, full - 0x2ffff) */
 
 #define CONFIG_EZYNQ_DUMP_DDR_LOW  0x4000000  /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
-#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff  /* DDR dump end   (deafault 0x40002ff) */
+#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x402ffff  /* DDR dump end   (deafault 0x40002ff) */
 #endif
 /* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
    If defined, each can be 0,1, ON or OFF */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_1   OFF /* in RBL setup, as soon as MIO is programmed, should be OFF to use GPIO */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_2   OFF /* First after getting to user code */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_3   ON  /* After setting clock registers */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_3   OFF  /* After setting clock registers */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_4   OFF /* After PLL bypass is OFF */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_5   ON  /* After UART is programmed */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_5   OFF  /* After UART is programmed */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_6   OFF /* After DCI is calibrated */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_7   ON  /* After DDR is initialized */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_7   OFF  /* After DDR is initialized */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_8   OFF /* Before relocation to DDR (to 0x4000000+ ) */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_9   ON  /* After  relocation to DDR (to 0x4000000+ ) */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_10  OFF /* Before remapping OCM0-OCM2 high */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_10  ON /* Before remapping OCM0-OCM2 high */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_11  ON  /* After remapping OCM0-OCM2 high */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_12  OFF /* Before leaving lowlevel_init() */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_12  ON /* Before leaving lowlevel_init() */
 #define CONFIG_EZYNQ_LAST_PRINT_DEBUG   y   /* 'Output to UART before exiting arch_cpu_init() */ 
 /* MIO configuration */
 #define CONFIG_EZYNQ_OCM                         /* not used */

u-boot-tree/include/configs/zynq_microzed.h

@@ -39,7 +39,7 @@
 #include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
 #include <configs/ezynq/zed_ezynq.h>
 
-#if 1
+#if 0
   #undef CONFIG_EZYNQ_BOOT_DEBUG        Y    /* configure UARTx and send register dumps there.*/
 #endif
 #define CONFIG_CMD_MEMTEST