Added expot of the debug LED control (d38a7e9f) · Commits · Elphel / ezynq

ezynq_clk.py

+32 −10

Original line number	Original line	Diff line number	Diff line
	@@ -92,6 +92,36 @@ class EzynqClk:
	self.clk_dict={}		self.clk_dict={}
	for c in CLK_TEMPLATE:		for c in CLK_TEMPLATE:
	self.clk_dict[c['NAME']]=c		self.clk_dict[c['NAME']]=c
			def generate_lock_unlock(self):
			# generate code to be included in u-boot to unlock SLCR before using it.
			# Should never be used in RBL - it will reset the system
			lock_register_set= ezynq_registers.EzynqRegisters(self.SLCR_CLK_DEFS,0,[])
			lock_register_set.set_word('slcr_lock',0x767b)
			lock_register_set.flush()
			lock_register_set.set_word('slcr_unlock',0xdf0d)
			return lock_register_set.get_register_sets(sort_addr=True,apply_new=True)


			#Unlock SLCR (if the code is running after RBL) - stage 0 of PLL setup
			def slcr_unlock(self):
			clk_register_set=self.clk_register_set
			if self.verbosity>0 :
			print 'Unlocking SLCR'
			clk_register_set.set_word('slcr_unlock',0xdf0d)
			def slcr_lock(self):
			clk_register_set=self.clk_register_set
			if self.verbosity>0 :
			print 'Unlocking SLCR'
			clk_register_set.set_word('slcr_lock',0x767b)

			# def clocks_regs_setup(self,current_reg_sets,unlock_needed=True,force=False,warn=False):
			# clk_register_set=self.clk_register_set
			# clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
			# if unlock_needed:
			# self.slcr_unlock()
			# clk_register_set.flush() # close previous register settings
			#

	def parse_parameters(self,raw_configs):		def parse_parameters(self,raw_configs):
	self.features.parse_features(raw_configs)		self.features.parse_features(raw_configs)
	def check_missing_features(self):		def check_missing_features(self):
	@@ -416,12 +446,10 @@ class EzynqClk:
	def get_new_register_sets(self):		def get_new_register_sets(self):
	return self.clk_register_set.get_register_sets(True,True)		return self.clk_register_set.get_register_sets(True,True)

	def clocks_regs_setup(self,current_reg_sets,unlock_needed=True,force=False,warn=False):
			def clocks_regs_setup(self,current_reg_sets,force=False,warn=False):
	clk_register_set=self.clk_register_set		clk_register_set=self.clk_register_set
	clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state		clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state
	if unlock_needed:
	self.slcr_unlock()
	clk_register_set.flush() # close previous register settings
	# Bypass used PLL-s - stage 1 of PLL setup		# Bypass used PLL-s - stage 1 of PLL setup
	self.clocks_pll_bypass(force=False,warn=False)		self.clocks_pll_bypass(force=False,warn=False)
	clk_register_set.flush() # close previous register settings		clk_register_set.flush() # close previous register settings
	@@ -438,12 +466,6 @@ class EzynqClk:
	self.clocks_program(force=False,warn=False)		self.clocks_program(force=False,warn=False)
	return self.get_new_register_sets()		return self.get_new_register_sets()

	#Unlock SLCR (if the code is running after RBL) - stage 0 of PLL setup
	def slcr_unlock(self):
	clk_register_set=self.clk_register_set
	if self.verbosity>0 :
	print 'Unlocking SLCR'
	clk_register_set.set_word('slcr_unlock',0xdf0d)

	#Bypass used PLL-s - stage 1 of PLL setup		#Bypass used PLL-s - stage 1 of PLL setup
	def clocks_pll_bypass(self,force=False,warn=False):		def clocks_pll_bypass(self,force=False,warn=False):

ezynq_mio.py

+12 −0

Original line number	Original line	Diff line number	Diff line
	@@ -287,6 +287,18 @@ class EzynqMIO:

	# self.DDRIOB_DEFS=ezynq_ddriob_def.DDRIOB_DEFS		# self.DDRIOB_DEFS=ezynq_ddriob_def.DDRIOB_DEFS
	# self.DDR_CFG_DEFS=ezynq_ddrcfg_defs.DDR_CFG_DEFS		# self.DDR_CFG_DEFS=ezynq_ddrcfg_defs.DDR_CFG_DEFS
			def generate_led_off_on(self, mio_pin):
			# generate code to be included in u-boot for debugging early boot stages
			led_register_set= ezynq_registers.EzynqRegisters(self.MIO_PINS_DEFS,0,[])
			led_register_set.set_bitfields('mio_pin_%02i'%mio_pin, ( # output 0 - LED off
			('pullup', 0),
			('tri_enable', 0))) # ,force,warn)
			led_register_set.flush()
			led_register_set.set_bitfields('mio_pin_%02i'%mio_pin, ( # input+pullup LED on
			('pullup', 1),
			('tri_enable', 1))) # ,force,warn)
			return led_register_set.get_register_sets(sort_addr=True,apply_new=True)

	def parse_config_mio(self,raw_configs):		def parse_config_mio(self,raw_configs):
	attrib_suffix='ATTRIB'		attrib_suffix='ATTRIB'
	options = {}		options = {}

ezynq_uboot.py

+67 −5

Original line number	Original line	Diff line number	Diff line
	@@ -66,6 +66,61 @@ class EzynqUBoot:
	self.cfile+='\twhile((readl(0x%08x) & %s) == %s); /* %s.%s %s */\n'%(addr,self._opt_hex(mask),self._opt_hex(data),module_name,register_name,comments)		self.cfile+='\twhile((readl(0x%08x) & %s) == %s); /* %s.%s %s */\n'%(addr,self._opt_hex(mask),self._opt_hex(data),module_name,register_name,comments)
	else:		else:
	raise Exception('Invalid register operation "%s" specified for register 0x%08x, data=0x%08x, mask=0x%08x'%(op,addr,data,mask))		raise Exception('Invalid register operation "%s" specified for register 0x%08x, data=0x%08x, mask=0x%08x'%(op,addr,data,mask))
			def make_slcr_lock_unlock(self, reg_sets):
			self.sections.append('slcr_lock_unlock_setup')
			self.cfile+="""
			/* Lock SLCR registers - may be called after everything is done. */
			void lock_slcr(void) /*not to conflict with another slcr_lock() in u-boot
			{
			"""
			self._add_reg_writes(reg_sets[:1])
			self.cfile+="""}

			/* Unlock SLCR registers - SHOULD be called first before writing any SLCR registers. */
			void unlock_slcr(void) /*not to conflict with another slcr_unlock() in u-boot
			{
			"""
			self._add_reg_writes(reg_sets[1:])
			self.cfile+='}\n'

			def make_led_on_off(self, reg_sets):
			self.sections.append('led_on_off')
			self.cfile+="""
			/* Turn LED on/off for debugging of the early stages of boot process. */
			void led_on_off(int on) /*not to conflict with another slcr_lock() in u-boot
			{
			"""
			self.cfile+='\tif (on)'
			self._add_reg_writes(reg_sets[1:])
			self.cfile+='\telse'
			self._add_reg_writes(reg_sets[:1])
			self.cfile+='}\n'

			#make_led_on_off
			# void led_off(void){
			# writel(0x00000200, &slcr_base->mio_pin[47]); /* LED off */
			# }
			# void led_on(void){
			# writel(0x00001201, &slcr_base->mio_pin[47]); /* LED on */
			# }
			#
			# void poll_fifo_empty(void){
			# while ((readl(&uart1_base->channel_sts) & 0x8) ==0) ; /* wait transmitter buffer is empty */
			# }
			#
			# void poll_putc(int d){
			# led_off();
			# while ((readl(&uart1_base->channel_sts) & 0x10) !=0) ; /* wait transmitter buffer is not full */
			# led_on();
			# writel(d, &uart1_base->tx_rx_fifo);
			# }
			# void poll_puts(char * line){
			# int i=0;
			# while (line[i]!=0) poll_putc(line[i++]);
			# }




	def registers_setup(self, reg_sets,clk,num_rbl_regs): #clk is an instance of ezynq_clk.EzynqClk		def registers_setup(self, reg_sets,clk,num_rbl_regs): #clk is an instance of ezynq_clk.EzynqClk
	self.sections.append('registers_setup')		self.sections.append('registers_setup')
	@@ -141,9 +196,15 @@ void lowlevel_init(void)
	'''		'''

	self.cfile+='''/*		self.cfile+='''/*
	Unlock SLCR and write PLL and clocks registers as the code is now running in the OCM and no		Unlock SLCR
	peripherals are needed
	*/		*/
			\tunlock_slcr();

			/*
			Write PLL and clocks registers as the code is now completely loaded to the OCM and no
			peripherals are needed immediately
			*/

	\tregister_setup();		\tregister_setup();

	/*		/*
	@@ -207,12 +268,13 @@ void lowlevel_init(void)
	\twritel(0x0, &slcr_base->ddr_urgent_sel);		\twritel(0x0, &slcr_base->ddr_urgent_sel);
	\t/* Urgent write, ports S2/S3 */		\t/* Urgent write, ports S2/S3 */
	\twritel(0xC, &slcr_base->ddr_urgent);		\twritel(0xC, &slcr_base->ddr_urgent);
	\tzynq_slcr_lock();		\tlock_slcr();
	/*		/*
	This code was called from low OCM, so return should just get back correctly		This code was called from low OCM, so return should just get back correctly
	*/		*/
	}		}
	'''		'''

	def output_c_file(self,cname):		def output_c_file(self,cname):
	if not cname:		if not cname:
	return		return

ezynqcfg.py

+28 −1

Original line number	Original line	Diff line number	Diff line
	@@ -348,7 +348,7 @@ else:

	#initialize clocks		#initialize clocks
	# unlock slcr - it is locked by RBL, but attempt to unlock in RBL will fail (and hang the system)		# unlock slcr - it is locked by RBL, but attempt to unlock in RBL will fail (and hang the system)
	reg_sets=clk.clocks_regs_setup(reg_sets,True,force)		reg_sets=clk.clocks_regs_setup(reg_sets,force)
	segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock registers configuration'})		segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock registers configuration'})
	#print 'Debug mode: CLK/PLL configuration by u-boot'		#print 'Debug mode: CLK/PLL configuration by u-boot'
	reg_sets=clk.clocks_pll_bypass_off(reg_sets,force)		reg_sets=clk.clocks_pll_bypass_off(reg_sets,force)
	@@ -383,6 +383,26 @@ if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:
	reg_sets=ddr.ddr_start(reg_sets,False,False)		reg_sets=ddr.ddr_start(reg_sets,False,False)
	segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})		segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})

			# Generate lock/unlock SLCR to be used in u-boot
			reg_sets_lock_unlock=clk.generate_lock_unlock()
			#print reg_sets[len(reg_sets)-1]
			reg_sets.extend (reg_sets_lock_unlock) # just to be listed, not to be loaded
			segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'SLCR_LOCK_UNLOCK','TITLE':'SLCR lock/unlock registers - listed out of sequence'})

			try:
			led_mio_pin=int (raw_config_value('CONFIG_EZYNQ_LED_DEBUG', raw_configs),0)
			reg_sets_led=mio_regs.generate_led_off_on(led_mio_pin)
			reg_sets.extend (reg_sets_led) # just to be listed, not to be loaded
			segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'LED','TITLE':'registers/data to turn on/off debug LED - listed out of sequence'})
			except:
			led_mio_pin=None
			# def generate_led_off_on(self, mio_pin):
			#CONFIG_EZYNQ_LED_DEBUG=47 # toggle LED during boot
			#CONFIG_EZYNQ_BOOT_DEBUG

			#print reg_sets_lock_unlock[0]
			#print reg_sets_lock_unlock[1]

	# make reg_sets data cumulative		# make reg_sets data cumulative
	reg_sets=ezynq_registers.accumulate_reg_data(reg_sets)		reg_sets=ezynq_registers.accumulate_reg_data(reg_sets)
	num_rbl_regs=0		num_rbl_regs=0
	@@ -410,6 +430,7 @@ for segment in segments:
	segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]),		segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]),
	show_bit_fields, show_comments, filter_fields)		show_bit_fields, show_comments, filter_fields)
	# print segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]), start,end		# print segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]), start,end

	ezynq_registers.print_html_registers(f,		ezynq_registers.print_html_registers(f,
	reg_sets[:end],		reg_sets[:end],
	start,		start,
	@@ -457,6 +478,12 @@ if args.outfile:
	# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})		# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})

	u_boot=ezynq_uboot.EzynqUBoot(args.verbosity)		u_boot=ezynq_uboot.EzynqUBoot(args.verbosity)

			if 'SLCR_LOCK_UNLOCK' in segment_dict:
			u_boot.make_slcr_lock_unlock (reg_sets[segment_dict['SLCR_LOCK_UNLOCK']['FROM']:segment_dict['SLCR_LOCK_UNLOCK']['TO']])
			if 'LED' in segment_dict:
			u_boot.make_led_on_off(reg_sets[segment_dict['LED']['FROM']:segment_dict['LED']['TO']])

	if 'CLK' in segment_dict:		if 'CLK' in segment_dict:
	u_boot.registers_setup (reg_sets[segment_dict['CLK']['FROM']:segment_dict['CLK']['TO']],clk,num_rbl_regs)		u_boot.registers_setup (reg_sets[segment_dict['CLK']['FROM']:segment_dict['CLK']['TO']],clk,num_rbl_regs)
	if 'PLL' in segment_dict:		if 'PLL' in segment_dict:

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