1. +SPL support: updated to u-boot-xlnx -b master-next 54fee227ef141214141a226efd17ae0516deaf32 (bbbfb42e) · Commits · Elphel / ezynq

ezynq_uboot.py

+6 −1

Original line number	Diff line number	Diff line
		@@ -133,6 +133,7 @@ class EzynqUBoot:
		#include <asm/io.h>
		#include <asm/arch/sys_proto.h>
		#include <asm/arch/hardware.h>
		#include <asm/arch/clk.h>

		"""

		@@ -761,6 +762,10 @@ int arch_cpu_init(void)
		if 'uart_xmit' in self.sections:
		self.cfile+='\tuart_wait_tx_fifo_empty(); /* Second time - for some reason 1 wait sometimes fails after LAST_PRINT_DEBUG */\n'

		self.cfile+='''/* set up the CPU clk clock frequency in the global data struct */
		zynq_clk_early_init();
		'''

		#LOCK_SLCR
		if self.features.get_par_value_or_none('LOCK_SLCR') is False:
		self.cfile+='/* Leaving SLCR registers UNLOCKED according to setting of %s */\n'%self.features.get_par_confname('LOCK_SLCR')

install_uboot.sh

+1 −1

Original line number	Diff line number	Diff line
		@@ -52,7 +52,7 @@ fi

		echo "Step 2: Checking out u-boot version with the hash 'bbd91fc9ae290c31dc52fd8322f43f67ddd39247'"
		cd "$REPO_DIR_NAME"
		git checkout bbd91fc9ae290c31dc52fd8322f43f67ddd39247
		git checkout 54fee227ef141214141a226efd17ae0516deaf32

		echo "Step 3: Merging ezynq with u-boot"

u-boot-tree/arch/arm/cpu/armv7/zynq/Makefile

+14 −45

Original line number	Diff line number	Diff line
		@@ -5,53 +5,22 @@
		# (C) Copyright 2008
		# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
		#
		# See file CREDITS for list of people who contributed to this
		# project.
		# SPDX-License-Identifier: GPL-2.0+
		#
		# This program is free software; you can redistribute it and/or
		# modify it under the terms of the GNU General Public License as
		# published by the Free Software Foundation; either version 2 of
		# the License, or (at your option) any later version.
		#
		# This program is distributed in the hope that it will be useful,
		# but WITHOUT ANY WARRANTY; without even the implied warranty of
		# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		# GNU General Public License for more details.
		#
		# You should have received a copy of the GNU General Public License
		# along with this program; if not, write to the Free Software
		# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
		# MA 02111-1307 USA
		#

		include $(TOPDIR)/config.mk

		LIB = $(obj)lib$(SOC).o
		obj-y := timer.o
		obj-y += cpu.o
		obj-y += ddrc.o
		obj-y += slcr.o

		COBJS-y := timer.o
		COBJS-y += cpu.o
		COBJS-y += ddrc.o
		COBJS-y += slcr.o
		ifneq ($(CONFIG_EZYNQ),)
		COBJS-y += ezynq.o
		#use CONFIG_EZYNQ for the first (spl) u-boot pass or the only one (if spl building disabled)
		ifeq ($(CONFIG_SPL),)
		obj-$(CONFIG_EZYNQ) += ezynq.o
		endif
		ifneq ($(CONFIG_SPL_BUILD),)
		obj-$(CONFIG_EZYNQ) += ezynq.o
		endif


		COBJS := $(COBJS-y)

		SRCS := $(COBJS:.o=.c)
		OBJS := $(addprefix $(obj),$(COBJS))

		all: $(obj).depend $(LIB)

		$(LIB): $(OBJS)
		$(call cmd_link_o_target, $(OBJS))

		#########################################################################

		# defines $(obj).depend target
		include $(SRCTREE)/rules.mk

		sinclude $(obj).depend

		#########################################################################
		obj-y += clk.o
		obj-y += lowlevel_init.o
		obj-$(CONFIG_SPL_BUILD) += spl.o

u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c

+22 −28

Original line number	Diff line number	Diff line
		@@ -2,37 +2,22 @@
		* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
		* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
		*
		* See file CREDITS for list of people who contributed to this
		* project.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License as
		* published by the Free Software Foundation; either version 2 of
		* the License, or (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
		* MA 02111-1307 USA
		* SPDX-License-Identifier: GPL-2.0+
		*/
		#include <common.h>
		#include <asm/io.h>
		#include <asm/arch/sys_proto.h>
		#include <asm/arch/hardware.h>
		#include <asm/arch/clk.h>

		void lowlevel_init(void)
		{
		}
		#ifndef CONFIG_EZYNQ
		int arch_cpu_init(void)
		#define ZYNQ_SILICON_VER_MASK 0xF0000000
		#define ZYNQ_SILICON_VER_SHIFT 28

		/* Added __weak because the function is overridden in ezynq.c */
		__weak int arch_cpu_init(void)
		{
		zynq_slcr_unlock();

		#ifndef CONFIG_SPL_BUILD
		/* Device config APB, unlock the PCAP */
		writel(0x757BDF0D, &devcfg_base->unlock);
		writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
		@@ -45,19 +30,28 @@ int arch_cpu_init(void)
		writel(0x1F, &slcr_base->ocm_cfg);
		/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
		writel(0x0, &slcr_base->fpga_rst_ctrl);
		/* TZ_DDR_RAM, Set DDR trust zone non-secure */
		writel(0xFFFFFFFF, &slcr_base->trust_zone);
		/* Set urgent bits with register */
		writel(0x0, &slcr_base->ddr_urgent_sel);
		/* Urgent write, ports S2/S3 */
		writel(0xC, &slcr_base->ddr_urgent);
		#endif

		#endif
		zynq_clk_early_init();
		zynq_slcr_lock();

		return 0;
		}
		#endif

		unsigned int zynq_get_silicon_version(void)
		{
		unsigned int ver;

		ver = (readl(&devcfg_base->mctrl) &
		ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;

		return ver;
		}

		void reset_cpu(ulong addr)
		{
		zynq_slcr_cpu_reset();

u-boot-tree/arch/arm/cpu/armv7/zynq/spl.c

0 → 100644

+95 −0

Original line number	Diff line number	Diff line
		/*
		* (C) Copyright 2014 Xilinx, Inc. Michal Simek
		*
		* SPDX-License-Identifier: GPL-2.0+
		*/
		#include <common.h>
		#include <spl.h>

		#include <asm/io.h>
		#include <asm/arch/hardware.h>
		#include <asm/arch/spl.h>
		#include <asm/arch/sys_proto.h>

		#ifndef CONFIG_EZYNQ
		__weak void ps7_init(void)
		{
		puts("Please copy ps7_init.c/h from hw project\n");
		}
		#endif

		DECLARE_GLOBAL_DATA_PTR;

		void board_init_f(ulong dummy)
		{
		/* Clear the BSS. */
		memset(__bss_start, 0, __bss_end - __bss_start);

		/* Set global data pointer. */
		gd = &gdata;

		#ifndef CONFIG_EZYNQ
		ps7_init();
		#endif
		preloader_console_init();
		arch_cpu_init();

		#ifdef CONFIG_EZYNQ
		puts("Copying ps7_init.c/h from hw project is NOT REQUIRED\n");
		#endif
		board_init_r(NULL, 0);
		}

		void spl_board_init(void)
		{
		board_init();
		}

		u32 spl_boot_device(void)
		{
		u32 mode;

		switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
		#ifdef CONFIG_SPL_SPI_SUPPORT
		case ZYNQ_BM_QSPI:
		puts("qspi boot\n");
		mode = BOOT_DEVICE_SPI;
		break;
		#endif
		case ZYNQ_BM_NAND:
		mode = BOOT_DEVICE_NAND;
		break;
		case ZYNQ_BM_NOR:
		mode = BOOT_DEVICE_NOR;
		break;
		#ifdef CONFIG_SPL_MMC_SUPPORT
		case ZYNQ_BM_SD:
		puts("mmc boot\n");
		mode = BOOT_DEVICE_MMC1;
		break;
		#endif
		case ZYNQ_BM_JTAG:
		mode = BOOT_DEVICE_RAM;
		break;
		default:
		puts("Unsupported boot mode selected\n");
		hang();
		}

		return mode;
		}

		#ifdef CONFIG_SPL_MMC_SUPPORT
		u32 spl_boot_mode(void)
		{
		return MMCSD_MODE_FAT;
		}
		#endif

		#ifdef CONFIG_SPL_OS_BOOT
		int spl_start_uboot(void)
		{
		/* boot linux */
		return 0;
		}
		#endif