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Elphel
ezynq
Commits
bbbfb42e
Commit
bbbfb42e
authored
Mar 07, 2014
by
Oleg Dzhimiev
Browse files
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Plain Diff
1. +SPL support: updated to u-boot-xlnx -b master-next 54fee227ef141214141a226efd17ae0516deaf32
parent
10bafcb2
Changes
13
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13 changed files
with
1738 additions
and
1651 deletions
+1738
-1651
ezynq_uboot.py
ezynq_uboot.py
+6
-1
install_uboot.sh
install_uboot.sh
+1
-1
Makefile
u-boot-tree/arch/arm/cpu/armv7/zynq/Makefile
+14
-45
cpu.c
u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c
+22
-28
spl.c
u-boot-tree/arch/arm/cpu/armv7/zynq/spl.c
+95
-0
Makefile
u-boot-tree/board/elphel/elphel393/Makefile
+5
-44
board.c
u-boot-tree/board/elphel/elphel393/board.c
+15
-35
boards.cfg
u-boot-tree/boards.cfg
+1227
-1158
elphel393.h
u-boot-tree/include/configs/elphel393.h
+81
-75
zynq_microzed.h
u-boot-tree/include/configs/zynq_microzed.h
+86
-92
zynq_zc706.h
u-boot-tree/include/configs/zynq_zc706.h
+84
-75
zynq_zed.h
u-boot-tree/include/configs/zynq_zed.h
+89
-91
makeuboot
u-boot-tree/makeuboot
+13
-6
No files found.
ezynq_uboot.py
View file @
bbbfb42e
...
...
@@ -133,6 +133,7 @@ class EzynqUBoot:
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
"""
...
...
@@ -760,7 +761,11 @@ int arch_cpu_init(void)
self
.
_cp_led
(
'LED_CHECKPOINT_12'
)
# Before leaving lowlevel_init()
if
'uart_xmit'
in
self
.
sections
:
self
.
cfile
+=
'
\t
uart_wait_tx_fifo_empty(); /* Second time - for some reason 1 wait sometimes fails after LAST_PRINT_DEBUG */
\n
'
self
.
cfile
+=
'''/* set up the CPU clk clock frequency in the global data struct */
zynq_clk_early_init();
'''
#LOCK_SLCR
if
self
.
features
.
get_par_value_or_none
(
'LOCK_SLCR'
)
is
False
:
self
.
cfile
+=
'/* Leaving SLCR registers UNLOCKED according to setting of
%
s */
\n
'
%
self
.
features
.
get_par_confname
(
'LOCK_SLCR'
)
...
...
install_uboot.sh
View file @
bbbfb42e
...
...
@@ -52,7 +52,7 @@ fi
echo
"Step 2: Checking out u-boot version with the hash 'bbd91fc9ae290c31dc52fd8322f43f67ddd39247'"
cd
"
$REPO_DIR_NAME
"
git checkout
bbd91fc9ae290c31dc52fd8322f43f67ddd39247
git checkout
54fee227ef141214141a226efd17ae0516deaf32
echo
"Step 3: Merging ezynq with u-boot"
...
...
u-boot-tree/arch/arm/cpu/armv7/zynq/Makefile
View file @
bbbfb42e
...
...
@@ -5,53 +5,22 @@
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
# SPDX-License-Identifier: GPL-2.0+
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include
$(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(SOC)
.o
obj-y
:=
timer.o
obj-y
+=
cpu.o
obj-y
+=
ddrc.o
obj-y
+=
slcr.o
COBJS-y
:=
timer.o
COBJS-y
+=
cpu.o
COBJS-y
+=
ddrc
.o
COBJS-y
+=
slcr.o
ifneq
($(CONFIG_
EZYNQ
),)
COBJS-y
+=
ezynq.o
#use CONFIG_EZYNQ for the first (spl) u-boot pass or the only one (if spl building disabled)
ifeq
($(CONFIG_SPL),)
obj-$(CONFIG_EZYNQ)
+=
ezynq
.o
endif
ifneq
($(CONFIG_
SPL_BUILD
),)
obj-$(CONFIG_EZYNQ)
+=
ezynq.o
endif
COBJS
:=
$
(
COBJS-y
)
SRCS
:=
$
(
COBJS:.o
=
.c
)
OBJS
:=
$
(
addprefix
$(obj)
,
$(COBJS)
)
all
:
$(obj).depend $(LIB)
$(LIB)
:
$(OBJS)
$
(
call cmd_link_o_target,
$(OBJS)
)
#########################################################################
# defines $(obj).depend target
include
$(SRCTREE)/rules.mk
sinclude
$(obj).depend
#########################################################################
obj-y
+=
clk.o
obj-y
+=
lowlevel_init.o
obj-$(CONFIG_SPL_BUILD)
+=
spl.o
u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c
View file @
bbbfb42e
...
...
@@ -2,37 +2,22 @@
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
void
lowlevel_init
(
void
)
{
}
#ifndef CONFIG_EZYNQ
int
arch_cpu_init
(
void
)
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
/* Added __weak because the function is overridden in ezynq.c */
__weak
int
arch_cpu_init
(
void
)
{
zynq_slcr_unlock
();
#ifndef CONFIG_SPL_BUILD
/* Device config APB, unlock the PCAP */
writel
(
0x757BDF0D
,
&
devcfg_base
->
unlock
);
writel
(
0xFFFFFFFF
,
&
devcfg_base
->
rom_shadow
);
...
...
@@ -45,19 +30,28 @@ int arch_cpu_init(void)
writel
(
0x1F
,
&
slcr_base
->
ocm_cfg
);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel
(
0x0
,
&
slcr_base
->
fpga_rst_ctrl
);
/* TZ_DDR_RAM, Set DDR trust zone non-secure */
writel
(
0xFFFFFFFF
,
&
slcr_base
->
trust_zone
);
/* Set urgent bits with register */
writel
(
0x0
,
&
slcr_base
->
ddr_urgent_sel
);
/* Urgent write, ports S2/S3 */
writel
(
0xC
,
&
slcr_base
->
ddr_urgent
);
#endif
#endif
zynq_clk_early_init
();
zynq_slcr_lock
();
return
0
;
}
#endif
unsigned
int
zynq_get_silicon_version
(
void
)
{
unsigned
int
ver
;
ver
=
(
readl
(
&
devcfg_base
->
mctrl
)
&
ZYNQ_SILICON_VER_MASK
)
>>
ZYNQ_SILICON_VER_SHIFT
;
return
ver
;
}
void
reset_cpu
(
ulong
addr
)
{
zynq_slcr_cpu_reset
();
...
...
@@ -71,4 +65,4 @@ void enable_caches(void)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable
();
}
#endif
\ No newline at end of file
#endif
u-boot-tree/arch/arm/cpu/armv7/zynq/spl.c
0 → 100644
View file @
bbbfb42e
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#ifndef CONFIG_EZYNQ
__weak
void
ps7_init
(
void
)
{
puts
(
"Please copy ps7_init.c/h from hw project
\n
"
);
}
#endif
DECLARE_GLOBAL_DATA_PTR
;
void
board_init_f
(
ulong
dummy
)
{
/* Clear the BSS. */
memset
(
__bss_start
,
0
,
__bss_end
-
__bss_start
);
/* Set global data pointer. */
gd
=
&
gdata
;
#ifndef CONFIG_EZYNQ
ps7_init
();
#endif
preloader_console_init
();
arch_cpu_init
();
#ifdef CONFIG_EZYNQ
puts
(
"Copying ps7_init.c/h from hw project is NOT REQUIRED
\n
"
);
#endif
board_init_r
(
NULL
,
0
);
}
void
spl_board_init
(
void
)
{
board_init
();
}
u32
spl_boot_device
(
void
)
{
u32
mode
;
switch
((
zynq_slcr_get_boot_mode
())
&
ZYNQ_BM_MASK
)
{
#ifdef CONFIG_SPL_SPI_SUPPORT
case
ZYNQ_BM_QSPI
:
puts
(
"qspi boot
\n
"
);
mode
=
BOOT_DEVICE_SPI
;
break
;
#endif
case
ZYNQ_BM_NAND
:
mode
=
BOOT_DEVICE_NAND
;
break
;
case
ZYNQ_BM_NOR
:
mode
=
BOOT_DEVICE_NOR
;
break
;
#ifdef CONFIG_SPL_MMC_SUPPORT
case
ZYNQ_BM_SD
:
puts
(
"mmc boot
\n
"
);
mode
=
BOOT_DEVICE_MMC1
;
break
;
#endif
case
ZYNQ_BM_JTAG
:
mode
=
BOOT_DEVICE_RAM
;
break
;
default:
puts
(
"Unsupported boot mode selected
\n
"
);
hang
();
}
return
mode
;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
u32
spl_boot_mode
(
void
)
{
return
MMCSD_MODE_FAT
;
}
#endif
#ifdef CONFIG_SPL_OS_BOOT
int
spl_start_uboot
(
void
)
{
/* boot linux */
return
0
;
}
#endif
u-boot-tree/board/elphel/elphel393/Makefile
View file @
bbbfb42e
...
...
@@ -2,50 +2,11 @@
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
# SPDX-License-Identifier: GPL-2.0+
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include
$(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(BOARD)
.o
COBJS-y
:=
board.o
COBJS
:=
$
(
sort
$
(
COBJS-y
))
SRCS
:=
$
(
COBJS:.o
=
.c
)
OBJS
:=
$
(
addprefix
$(obj)
,
$(COBJS)
)
$(LIB)
:
$(obj).depend $(OBJS)
$
(
call cmd_link_o_target,
$(OBJS)
)
clean
:
rm
-f
$(OBJS)
distclean
:
clean
rm
-f
$(LIB)
core
*
.bak
$(obj)
.depend
#########################################################################
# defines $(obj).depend target
include
$(SRCTREE)/rules.mk
sinclude
$(obj).depend
obj-y
:=
board.o
#########################################################################
ifeq
($(CONFIG_SPL_BUILD),y)
$(shell
touch
xil_io.h)
endif
u-boot-tree/board/elphel/elphel393/board.c
View file @
bbbfb42e
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
...
...
@@ -29,19 +13,13 @@
DECLARE_GLOBAL_DATA_PTR
;
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
#define QSPI_MODE 0x00000001
#define NOR_FLASH_MODE 0x00000002
#define NAND_FLASH_MODE 0x00000004
#define SD_MODE 0x00000005
#define JTAG_MODE 0x00000000
#ifdef CONFIG_FPGA
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
Xilinx_desc
fpga
;
/* It can be done differently */
Xilinx_desc
fpga010
=
XILINX_XC7Z010_DESC
(
0x10
);
Xilinx_desc
fpga015
=
XILINX_XC7Z015_DESC
(
0x15
);
Xilinx_desc
fpga020
=
XILINX_XC7Z020_DESC
(
0x20
);
Xilinx_desc
fpga030
=
XILINX_XC7Z030_DESC
(
0x30
);
Xilinx_desc
fpga045
=
XILINX_XC7Z045_DESC
(
0x45
);
...
...
@@ -59,6 +37,9 @@ int board_init(void)
case
XILINX_ZYNQ_7010
:
fpga
=
fpga010
;
break
;
case
XILINX_ZYNQ_7015
:
fpga
=
fpga015
;
break
;
case
XILINX_ZYNQ_7020
:
fpga
=
fpga020
;
break
;
...
...
@@ -79,7 +60,8 @@ int board_init(void)
*/
writel
(
0x26d
,
0xe0001014
);
#ifdef CONFIG_FPGA
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init
();
fpga_add
(
fpga_xilinx
,
&
fpga
);
#endif
...
...
@@ -88,20 +70,20 @@ int board_init(void)
int
board_late_init
(
void
)
{
switch
((
zynq_slcr_get_boot_mode
())
&
BOOT_MODES
_MASK
)
{
case
QSPI_MODE
:
switch
((
zynq_slcr_get_boot_mode
())
&
ZYNQ_BM
_MASK
)
{
case
ZYNQ_BM_QSPI
:
setenv
(
"modeboot"
,
"qspiboot"
);
break
;
case
NAND_FLASH_MODE
:
case
ZYNQ_BM_NAND
:
setenv
(
"modeboot"
,
"nandboot"
);
break
;
case
NOR_FLASH_MODE
:
case
ZYNQ_BM_NOR
:
setenv
(
"modeboot"
,
"norboot"
);
break
;
case
SD_MODE
:
case
ZYNQ_BM_SD
:
setenv
(
"modeboot"
,
"sdboot"
);
break
;
case
JTAG_MODE
:
case
ZYNQ_BM_JTAG
:
setenv
(
"modeboot"
,
"jtagboot"
);
break
;
default:
...
...
@@ -112,7 +94,6 @@ int board_late_init(void)
return
0
;
}
#ifdef CONFIG_CMD_NET
int
board_eth_init
(
bd_t
*
bis
)
{
u32
ret
=
0
;
...
...
@@ -146,7 +127,6 @@ int board_eth_init(bd_t *bis)
#endif
return
ret
;
}
#endif
#ifdef CONFIG_CMD_MMC
int
board_mmc_init
(
bd_t
*
bd
)
...
...
u-boot-tree/boards.cfg
View file @
bbbfb42e
This source diff could not be displayed because it is too large. You can
view the blob
instead.
u-boot-tree/include/configs/elphel393.h
View file @
bbbfb42e
...
...
@@ -19,30 +19,21 @@
#ifndef __CONFIG_ELPHEL393_H
#define __CONFIG_ELPHEL393_H
/*#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) */
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART0
#if 1
//#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
//#define CONFIG_ZYNQ_SPI
#define CONFIG_DEFAULT_DEVICE_TREE zynq-elphel393
/* #define CONFIG_NAND_ZYNQ */
/* With NAND 0x31048. no memtest - 0x30d20, undef CONFIG_CMDLINE_EDITING - 0x30468 */
#undef CONFIG_SYS_TEXT_BASE
#include <configs/zynq_common.h>
#undef CONFIG_IPADDR
#undef CONFIG_SERVERIP
#include <configs/zynq-common.h>
#undef CONFIG_SYS_PROMPT
#undef CONFIG_BOOTDELAY
#undef CONFIG_EXTRA_ENV_SETTINGS
#include <configs/ezynq/ezynq_MT41K256M16HA107.h>
/* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_XC7Z030_1FBG484C.h>
...
...
@@ -50,91 +41,106 @@
#define CONFIG_CMD_MEMTEST
/* twice slower */
#undef CONFIG_ZYNQ_SERIAL_CLOCK0
/*#define CONFIG_ZYNQ_SERIAL_CLOCK0 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK0 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_ZYNQ_SERIAL_CLOCK1
/*#define CONFIG_ZYNQ_SERIAL_CLOCK1 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK1 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_BOOTDELAY
#undef CONFIG_SYS_PROMPT
#undef CONFIG_SYS_SDRAM_BASE
#undef CONFIG_ENV_SIZE
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTDELAY 1
/* -1 to Disable autoboot */
#define CONFIG_SYS_PROMPT "elphel393-u-boot> "
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Physical start address of SDRAM. _Must_ be 0 here. */
#define CONFIG_ENV_SIZE 1400
#define CONFIG_SYS_TEXT_BASE 0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
/*
#define CONFIG_EZYNQ_SKIP_DDR
*/
/*#define CONFIG_EZYNQ_SKIP_DDR*/
#define CONFIG_EZYNQ_SKIP_CLK
//undefs
/* undefs */
/*#undef CONFIG_FS_FAT */
/* #undef CONFIG_SUPPORT_VFAT */
/* #undef CONFIG_CMD_FAT */
/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
/* CONFIG_FS_FAT=y */
/* disable PL*/
#undef CONFIG_FPGA
#undef CONFIG_FPGA_XILINX
#undef CONFIG_FPGA_ZYNQPL
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_EXT2
#undef CONFIG_CMD_CACHE
#undef DEBUG
#undef CONFIG_AUTO_COMPLETE
#undef CONFIG_SYS_LONGHELP
/*#undef CONFIG_CMDLINE_EDITING */
/* redefine env settings*/
#undef CONFIG_EXTRA_ENV_SETTINGS
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"ethaddr=00:0a:35:00:01:22\0" \
"kernel_image=uImage\0" \
"ramdisk_image=uramdisk.image.gz\0" \
"devicetree_image=devicetree.dtb\0" \
"bitstream_image=system.bit.bin\0" \
"boot_image=BOOT.bin\0" \
"loadbit_addr=0x100000\0" \
"loadbootenv_addr=0x2000000\0" \
"kernel_size=0x500000\0" \
"devicetree_size=0x20000\0" \
"ramdisk_size=0x5E0000\0" \
"boot_size=0xF00000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
"importbootenv=echo Importing environment from SD ...; " \
"env import -t ${loadbootenv_addr} $filesize\0" \
"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
"mmcinfo && " \
"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
"fpga load 0 ${loadbit_addr} ${filesize}\0" \
"sdboot=echo Copying Linux from SD to RAM... && " \
"mmcinfo && " \
"fatload mmc 0 0x3F00000 ${kernel_image} && " \
"fatload mmc 0 0x3E00000 ${devicetree_image} && " \
"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3F00000 0x2000000 0x3E00000\0" \
"norboot=echo Copying Linux from NOR flash to RAM... && " \
"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
"sf probe 0 0 0 && " \
"sf read 0x3000000 0x100000 ${kernel_size} && " \
"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"uenvboot=" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv}; " \
"run importbootenv; " \
"fi; " \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...; " \
"run uenvcmd; " \
"fi\0" \
"sdboot=if mmcinfo; then " \
"run uenvboot; " \
"echo Copying Linux from SD to RAM... && " \
"fatload mmc 0 0x3F00000 ${kernel_image} && " \
"fatload mmc 0 0x3E00000 ${devicetree_image} && " \
"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3F00000 0x2000000 0x3E00000; " \
"fi\0" \
"usbboot=if usb start; then " \
"run uenvboot; " \
"echo Copying Linux from USB to RAM... && " \
"fatload usb 0 0x3000000 ${kernel_image} && " \
"fatload usb 0 0x2A00000 ${devicetree_image} && " \
"fatload usb 0 0x2000000 ${ramdisk_image} && " \
"bootm 0x3000000 0x2000000 0x2A00000; " \
"fi\0" \
"nandboot=echo Copying Linux from NAND flash to RAM... && " \
"nand read 0x3000000 0x100000 ${kernel_size} && " \
"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
"echo Copying ramdisk... && " \
"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"jtagboot=echo TFTPing Linux to RAM... && " \
"tftpboot 0x3000000 ${kernel_image} && " \
"tftpboot 0x2A00000 ${devicetree_image} && " \
"tftpboot 0x2000000 ${ramdisk_image} && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
"cp.b 0xE2100000 0x100000 ${boot_size} && " \
"zynqrsa 0x100000 && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
"nand read 0x100000 0x0 ${boot_size} && " \
"zynqrsa 0x100000 && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
"sf probe 0 0 0 && " \
"sf read 0x100000 0x0 ${boot_size} && " \
"zynqrsa 0x100000 && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"rsa_sdboot=echo Copying Image from SD to RAM... && " \
"fatload mmc 0 0x100000 ${boot_image} && " \
"zynqrsa 0x100000 && " \
"bootm 0x3000000 0x2000000 0x2A00000\0" \
"rsa_jtagboot=echo TFTPing Image to RAM... && " \
"tftpboot 0x100000 ${boot_image} && " \
"zynqrsa 0x100000 && " \
"bootm 0x3000000 0x2000000 0x2A00000\0"
/* */
#endif
/* __CONFIG_ELPHEL393_H */
u-boot-tree/include/configs/zynq_microzed.h
View file @
bbbfb42e
/*
* (C) Copyright 201
2 Xilinx
* (C) Copyright 201
3 Xilinx, Inc.
*
* Configuration for
Zynq Evaluation and Development Board -
ZedBoard
* See zynq
_
common.h for Zynq common configs
* Configuration for
Micro Zynq Evaluation and Development Board - Micro
ZedBoard
* See zynq
-
common.h for Zynq common configs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQ_MICROZED_H
#define __CONFIG_ZYNQ_MICROZED_H
/*#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) */
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_SERIAL_UART1
#if 1
//#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
/* #define CONFIG_ZYNQ_SPI */
/* #define CONFIG_NAND_ZYNQ */
#undef CONFIG_SYS_TEXT_BASE
#include <configs/zynq_common.h>
#define CONFIG_DEFAULT_DEVICE_TREE zynq-microzed
#undef CONFIG_IPADDR
#undef CONFIG_SERVERIP
#include <configs/zynq-common.h>
#undef CONFIG_SYS_PROMPT
#undef CONFIG_BOOTDELAY
#undef CONFIG_EXTRA_ENV_SETTINGS
#include <configs/ezynq/ezynq_MT41K256M16RE125.h>
/* should be before
zed_ezynq
.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_MT41K256M16RE125.h>
/* should be before
ezynq_microzed
.h as it overwrites DDR3L with DDR3 */
#include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
#include <configs/ezynq/ezynq_microzed.h>
#if 0
#undef CONFIG_EZYNQ_BOOT_DEBUG /* configure UARTx and send register dumps there.*/
#endif
#define CONFIG_CMD_MEMTEST
/* twice slower */
#undef CONFIG_ZYNQ_SERIAL_CLOCK0
/*#define CONFIG_ZYNQ_SERIAL_CLOCK0 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK0 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_ZYNQ_SERIAL_CLOCK1
/*#define CONFIG_ZYNQ_SERIAL_CLOCK1 25000000*/
#define CONFIG_ZYNQ_SERIAL_CLOCK1 1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
#undef CONFIG_BOOTDELAY
#undef CONFIG_SYS_PROMPT
#undef CONFIG_SYS_SDRAM_BASE
#undef CONFIG_ENV_SIZE
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_BOOTDELAY 1
/* -1 to Disable autoboot */
#define CONFIG_SYS_PROMPT "microzed-u-boot> "
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Physical start address of SDRAM. _Must_ be 0 here. */
#define CONFIG_ENV_SIZE 1400
#if 0
#define CONFIG_SYS_TEXT_BASE 0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000
#endif
/*
#define CONFIG_EZYNQ_SKIP_DDR
*/
/*#define CONFIG_EZYNQ_SKIP_DDR*/
#define CONFIG_EZYNQ_SKIP_CLK
/* undefs */
/* undefs */
/*#undef CONFIG_FS_FAT */
/* #undef CONFIG_SUPPORT_VFAT */
/* #undef CONFIG_CMD_FAT */
/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
/* CONFIG_FS_FAT=y */