Commit b833a922 authored by Andrey Filippov's avatar Andrey Filippov

working version before adding generation of the C-file for u-boot

parent e368919b
......@@ -1426,7 +1426,10 @@ class EzynqDDR:
('drive_p',self.features.get_par_value('BIDIR_DRIVE_POS'))),force,warn) #0xf9861c
#Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?)
# ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0 (first time only?)
#
# Do in u-boot. When moving - use UG585 table 10-7 to set options
#
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)
_ = ddriob_register_set.get_register_sets(True,True) # close previous register settings
ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)
......
......@@ -187,8 +187,9 @@ DDRIOB_DEFS={ #not all fields are defined currently
'vrp_tri': {'r':( 2, 2),'d':0, 'c':'Reserved'},
'enable': {'r':( 1, 1),'d':0, 'c':'DCI System enable. Silicon v2+ require set to 1'}, #1
'reset': {'r':( 0, 0),'d':0, 'c':'Toggle once to initialize FF-s in DCI system.'}}}, #1
# reset is mentioned as DDRIOB_DCI_CNTRL_RESET_B , so it is active LOW
'ddriob_dci_status': {'OFFS': 0xb74,'DFLT':0x0,'RW':'RW', #0x823
'COMMENTS':'DDR IOB buffer control',
'COMMENTS':'DDR IOB buffer DCI status',
'FIELDS':{
'reserved1': {'r':(14,31),'d':0,'m':'R', 'c':'Reserved'},
'done': {'r':(13,13),'d':0, 'c':'DCI done'},
......
......@@ -35,6 +35,7 @@ parser.add_argument('-w', '--warn', help='Warn when the pin function is ove
parser.add_argument('-o', '--outfile', help='Path to save the generated boot file')
parser.add_argument('--html', help='Generate HTML map of MIO, save to the specified file')
parser.add_argument('--html-mask', help='Bit mask of what data to include in the HTML MIO map')
parser.add_argument('-i', '--include', help='Generate include file for u-boot')
args = parser.parse_args()
#print args
......@@ -260,6 +261,18 @@ def image_generator (image,
waddr+=1
image[waddr]=0
waddr+=1
# for addr, data, mask, module_name, register_name, r_def in reg_sets:
def write_include(filename,reg_sets):
incl_file=open(filename,'w')
# for addr, data, mask, module_name, register_name, r_def in reg_sets:
for addr, data, _, module_name, register_name, r_def in reg_sets:
try:
comments=r_def['COMMENTS']
except:
comments=''
incl_file.write(' writel(0x%08x, 0x%08x); /* %s.%s %s */\n'%(data,addr,module_name,register_name,comments))
incl_file.close()
def write_image(image,name):
bf=open(name,'wb')
......@@ -276,7 +289,13 @@ def write_image(image,name):
# data=s.pack(*image)
bf.write(data)
bf.close()
def raw_config_value(key, raw_config):
for kv in raw_config:
if kv['KEY']== key:
return kv['VALUE']
return None
#=========================
if not args.verbosity:
args.verbosity=0
......@@ -336,25 +355,36 @@ reg_sets=mio_regs.setregs_mio(reg_sets,force) # reg Sets include now MIO
num_mio_regs=len(reg_sets)
#adding ddr registers
ddr.ddr_init_memory(reg_sets,False,False)
reg_sets=ddr.get_new_register_sets() # mio, ddr
if raw_config_value('CONFIG_EZYNQ_SKIP_DDR', raw_configs) is None:
ddr.ddr_init_memory(reg_sets,False,False)
reg_sets=ddr.get_new_register_sets() # mio, ddr
else:
print 'Debug mode: skipping DDR-related configuration'
num_ddr_regs=len(reg_sets)-num_mio_regs
#define CONFIG_EZYNQ_SKIP_DDR
#define CONFIG_EZYNQ_SKIP_CLK
#initialize clocks
# def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
#if raw_config_value('CONFIG_EZYNQ_SKIP_CLK', raw_configs) is None:
clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK
reg_sets=clk.get_new_register_sets() # mio, ddr and clk
#else:
# print 'Debug mode: skipping CLK/PLL configuration'
num_clk_regs=len(reg_sets)-num_mio_regs-num_ddr_regs
if raw_config_value('CONFIG_EZYNQ_SKIP_CLK', raw_configs) is None:
num_rbl_regs=len(reg_sets)
print 'Debug mode: CLK/PLL configuration by RBL'
else:
num_rbl_regs=len(reg_sets)-num_clk_regs
print 'Debug mode: CLK/PLL configuration by u-boot'
# #adding ddr registers
# ddr.ddr_init_memory(reg_sets,False,False)
# #Collecting registers for output
#
# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr
ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
......@@ -369,48 +399,24 @@ ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs:num_mio_regs+num_d
ezynq_registers.print_html_reg_footer(f)
ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_ddr_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_ddr_regs:num_rbl_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
# #initialize clocks
# # def clocks_rbl_setup(self,current_reg_sets,force=False,warn=False):
#
# clk.clocks_rbl_setup(reg_sets,force) # reg Sets include now MIO and CLK
# reg_sets=clk.get_new_register_sets() # mio and clk
# num_clk_regs=len(reg_sets)-num_mio_regs
#
#
# #adding ddr registers
# ddr.ddr_init_memory(reg_sets,False,False)
# #Collecting registers for output
#
# reg_sets=ddr.get_new_register_sets() #all - mio,clk and ddr
#
#
# ezynq_registers.print_html_reg_header(f, 'MIO registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#
# #ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[:num_mio_regs], MIO_HTML_MASK & 0x800, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
#
# ezynq_registers.print_html_reg_header(f, 'CLOCK registers configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs: num_mio_regs+num_clk_regs], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
#
#
# ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_registers(f, reg_sets[num_mio_regs+num_clk_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
# ezynq_registers.print_html_reg_footer(f)
if len(reg_sets)>num_rbl_regs:
ezynq_registers.print_html_reg_header(f, 'Registers configuration in u-boot', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets[num_rbl_regs:], MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_reg_footer(f)
#TODO: Need to be modified for the new format
# if 'CONFIG_EZYNQ_UART_LOOPBACK_0' in raw_options: uart_remote_loopback(registers,f, 0,MIO_HTML_MASK)
# if 'CONFIG_EZYNQ_UART_LOOPBACK_1' in raw_options: uart_remote_loopback(registers,f, 1,MIO_HTML_MASK)
if f:
f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(len(reg_sets))+"</b> of maximal 256</h4>")
f.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>")
if num_rbl_regs<len(reg_sets):
f.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b> of maximal 256</h4>")
#
if MIO_HTML:
f.close
#if args.verbosity >= 1:
......@@ -424,7 +430,7 @@ image =[ 0 for k in range (0x8c0/4)]
#CONFIG_EZYNQ_START_EXEC= 0x20 # number of bytes to load to the OCM memory, <= 0x30000
image_generator (image,
reg_sets, #
reg_sets[:num_rbl_regs], #
#registers,
raw_options,
int(raw_options['CONFIG_EZYNQ_BOOT_USERDEF'],0), # user_def
......@@ -433,6 +439,9 @@ image_generator (image,
int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec)
if args.outfile:
write_image(image,args.outfile)
if args.include and (num_rbl_regs<len(reg_sets)):
write_include(args.include,reg_sets[num_rbl_regs:])
print 'Debug mode: writing u-boot setup registers to ',args.include
# print int(hex(1234567),0) # works for decimal and hex
# binary i/o - tutorial 11.3
......@@ -288,8 +288,13 @@ CONFIG_EZYNQ_CLK_TRACE_SRC = IO # Trace Port clock source (normally IO PLL)
# Even if memory itself is DDR3L (1.35V) it also can support DDR3 mode (1.5V). And unfortunately Zynq has degraded
# specs at 1.35V (only 400MHz maximal clock), so datasheets's 'DDR3L' should be replaced with 'DDR3' and the board
# power supply should be 1.5V - in that case 533MHz clock is possible
CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE = DDR3 # DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V)
##### performance data, final values (overwrite calculated) #####
CONFIG_EZYNQ_CLK_SPEED_GRADE = 3 # Device speed grade
#CONFIG_EZYNQ_CLK_PLL_MAX_MHZ = 1800.0 # Maximal PLL clock frequency, MHz. Overwrites default for selected speed grade: (Speed grade -1:1600, -2:1800, -3:2000)'},
......@@ -319,3 +324,5 @@ CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ = 444.0 # Maximal DDR_2X clock frequency (M
CONFIG_EZYNQ_CLK_COMPLIANCE_PERCENT = 5.0 # Allow exceeding maximal limits by this margin (percent'},
#CONFIG_EZYNQ_SKIP_DDR = y
CONFIG_EZYNQ_SKIP_CLK = y
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