Commit a3f7f58e authored by Eyesisbox Elphel's avatar Eyesisbox Elphel

continue on DDR initialization

parent 496a0d6f
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#!/usr/bin/env python
# Copyright (C) 2013, Elphel.inc.
# process configuration of features
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2013, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
class EzynqFeatures:
#Modify for this class
ERRORS={
'ERR_NOT_A_VARIANT': 'Specified value is not a valid variant',
'ERR_NOT_AN_INTEGER': 'Value is not an integer',
'ERR_NOT_A_FLOAT': 'Value is not a float',
'ERR_NOT_A_BOOLEAN': 'Value is not a boolean'
}
BOOLEANS=(('0','FALSE','DISABLE','DISABLED','N'),
('1','TRUE', 'ENABLE','ENABLED','Y'))
# defines - a list, order determines HTML output order
# Each element has fields:
# 'NAME' - unique name to access this parameter
# 'CONF_NAME' - how it appears in configuration file, '@' may be replaced by str(channel)
# 'TYPE' - either "I" for integer, F - float, T - text, B- boolean (may be false/true, 0/1 or enable{d}/disable{d} or tuple with valid options for value
# 'MANDATORY' - boolean: this parameter is mandatory (either directly specified or derived from some others)
# 'DERIVED' - TBD later
# 'DEFAULT' - default value (to be suggested on error? Use if not mandatory parameter?
# 'DESCRIPTION' - Parameter description - use in error message?
def _choice_val(self,t,value):
if isinstance(t,tuple) :
for c in t:
if isinstance(c,int):
try:
if (c==int(value,0)):
return c
except:
pass
elif isinstance(c,float):
try:
if (c==float(value)):
return c
except:
pass
elif isinstance(c, bool):
if value in self.BOOLEANS[1]:
return True
elif value in self.BOOLEANS[0]:
return False
elif isinstance(c, str):
return value
else:
return None
def __init__(self,defines,channel=0):
self.defs={}
for i,feature in enumerate(defines):
self.defs[feature['NAME']]=feature
self.defs[feature['NAME']]['INDEX']=i
self.channel=channel
self.pars={}
self.config_names={}
self.defined=[]
for name in self.defs:
cn=self.defs[name];
self.config_names[cn['CONF_NAME'].replace('@',str(channel))]=name
def parse_features(self,raw_configs):
for line in raw_configs:
conf_name = line['KEY']
value = line['VALUE']
value=str(value).upper()
try:
name=self.config_names[conf_name]
except:
continue
feature= self.defs[name]
if (value=='HELP'):
try:
print conf_name+': '+feature['DESCRIPTION']
except:
print conf_name+': description is not available'
continue
if isinstance(feature['TYPE'], tuple):
val=self._choice_val(feature['TYPE'],value)
if val==None:
raise Exception(self.BOOLEANS['ERR_NOT_A_VARIANT']+': '+line['VALUE'] +' is not a valid variant for parameter '+
conf_name+'. Valid are:'+str(feature['TYPE']))
else:
value=val
elif (feature['TYPE']=='I') or (feature['TYPE']=='H'):
try:
value= int(value,0)
except:
raise Exception(self.ERRORS['ERR_NOT_AN_INTEGER']+': '+line['VALUE'] +' is not a valid INTEGER value for parameter '+ conf_name)
elif (feature['TYPE']=='F'):
try:
value= float(value)
except:
raise Exception(self.ERRORS['ERR_NOT_A_FLOAT']+': '+line['VALUE'] +' is not a valid FLOAT value for parameter '+ conf_name)
elif (feature['TYPE']=='B'):
if value in self.BOOLEANS[1]:
value=True
elif value in self.BOOLEANS[0]:
value=False
else:
# print line['VALUE'],type(line['VALUE'])
# print line['VALUE'] in self.BOOLEANS[1]
raise Exception(self.ERRORS['ERR_NOT_A_BOOLEAN']+': '+line['VALUE'] +' is not a valid boolean value for parameter '+ conf_name+
'. Valid for "True" are:'+str(self.BOOLEANS[1])+', for "False" - '+str(self.BOOLEANS[0]))
elif (feature['TYPE']=='T'):
pass #keep string value
self.pars[name]=value
self.defined.append(name)
#check after calculating derivative parameters
def check_missing_features(self):
all_set=True
for name in self.defs:
if (not name in self.pars):
if self.defs[name]['MANDATORY']:
all_set=False
print "Configuration file is missing mandatory parameter "+self.defs[name]['CONF_NAME']+': '+self.defs[name]['DESCRIPTION']
else:
# use default parameter
# print 'Adding default : ',name,'=', self.defs[name]['DEFAULT']
self.pars[name]=self.defs[name]['DEFAULT']
return all_set
def get_par_names(self):
# name_offs=sorted([(name,self.registers[name]['OFFS']) for name in self.registers], key = lambda l: l[1])
# print '---self.registers=',self.registers
# unsorted_name_offs=[(name,self.defs[name]['OFFS']) for name in self.registers]
# print '---unsorted_name_offs=',unsorted_name_offs
# name_offs=sorted(unsorted_name_offs, key = lambda l: l[1])
# print '---name_offs=',name_offs
# return [n for n in name_offs]
# sort register names in the order of addresses
# name_index=sorted([(name,self.defs[name]['INDEX']) for name in self.pars], key = lambda l: l[1])
# return [n for n in sorted([(name,self.defs[name]['OFFS']) for name in self.registers], key = lambda l: l[1])]
return [n[0] for n in sorted([(name,self.defs[name]['INDEX']) for name in self.pars], key = lambda l: l[1])]
#TODO: Use SELECT for options?
def get_par_value(self,name):
try:
return self.pars[name]
except:
print 'name=',name
print self.pars
raise Exception (name+' not found in self.pars')
def html_list_features(self,html_file):
html_file.write('<table border="1">\n')
html_file.write('<tr><th>Configuration name</th><th>Value</th><th>Type/<br/>Choices</th><th>Mandatory</th><th>Derived</th><th>Default</th><th>Description</th></tr>\n')
# print self.get_par_names()
# for name in self.pars:
for name in self.get_par_names():
# name= self.config_names[conf_name]
feature= self.defs[name]
value= self.get_par_value(name)
if isinstance(value,int):
if (feature['TYPE']=='H'):
value=hex(value)
else:
value=str(value)
derived= not name in self.defined
if isinstance (feature['TYPE'],tuple):
par_type='<select>\n'
for t in feature['TYPE']:
par_type+=' <option>'+str(t)+'</option>\n'
# par_type+=('','<br/>')[i>0]+str(t)
par_type+='</select>\n'
else:
par_type={'H':'Integer','I':'Integer','F':'Float','B':'Boolean','T':'Text'}[feature['TYPE']]
html_file.write('<tr><th>'+feature['CONF_NAME']+'</th><td>'+str(value)+'</td><td>'+par_type+
'</td><td>'+('-','Y')[feature['MANDATORY']]+'</td><td>'+('-','Y')[derived]+'</td><td>'+str(feature['DEFAULT'])+'</td><td>'+feature['DESCRIPTION']+'</td></tr>\n')
html_file.write('</table>\n')
\ No newline at end of file
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...@@ -23,6 +23,7 @@ __email__ = "andrey@elphel.com" ...@@ -23,6 +23,7 @@ __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
import struct import struct
import ezynq_ddr import ezynq_ddr
import ezynq_registers
# http://docs.python.org/2/howto/argparse.html # http://docs.python.org/2/howto/argparse.html
import argparse import argparse
...@@ -943,9 +944,11 @@ raw_configs=read_config(args.configs) ...@@ -943,9 +944,11 @@ raw_configs=read_config(args.configs)
permit_undefined_bits=False permit_undefined_bits=False
force=True #False force=True #False
warn_notfit=True # False warn_notfit=True # False
regs_masked=[]
ddr=ezynq_ddr.EzynqDDR(permit_undefined_bits, force, warn_notfit) ddr=ezynq_ddr.EzynqDDR(regs_masked,permit_undefined_bits, force, warn_notfit)
ddr.parse_raw_register_set(raw_configs,QUALIFIER_CHAR,force,warn_notfit) ddr.parse_parameters(raw_configs)
##ddr.parse_ddriob_raw_register_set(raw_configs,QUALIFIER_CHAR,force,warn_notfit)
##ddr.parse_ddrc_raw_register_set(raw_configs,QUALIFIER_CHAR,force,warn_notfit)
#ddr.print_html_registers(html_file, show_bit_fields=True, show_comments=True) #ddr.print_html_registers(html_file, show_bit_fields=True, show_comments=True)
#class EzynqDDR: #class EzynqDDR:
# def __init__(self,permit_undefined_bits=False,force=False,warn=False): # def __init__(self,permit_undefined_bits=False,force=False,warn=False):
...@@ -999,7 +1002,26 @@ else: ...@@ -999,7 +1002,26 @@ else:
#output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL #output_slcr_lock(registers,f,False,MIO_HTML_MASK) #prohibited by RBL
output_mio(registers,f,mio,MIO_HTML_MASK) output_mio(registers,f,mio,MIO_HTML_MASK)
ddr.print_html_registers(f, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200) ddr.check_missing_features()
ddr.html_list_features(f)
#ddr.ddr_init_memory(current_reg_sets,force=False,warn=False): # will program to sequence 'MAIN'
ddr.ddr_init_memory([],False,False) # will program to sequence 'MAIN'
reg_sets=ddr.get_new_register_sets()
#ezynq_registers.print_html_reg_header(f, title, show_bit_fields=True, show_comments=True,filter_fields=True)
ezynq_registers.print_html_reg_header(f, 'DDR Configuration', MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
ezynq_registers.print_html_registers(f, reg_sets, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400)
#print_html_registers(html_file, reg_sets, show_bit_fields=True, show_comments=True,filter_fields=True):
ezynq_registers.print_html_reg_footer(f)
#ddr.print_html_registers(f, MIO_HTML_MASK & 0x100, MIO_HTML_MASK & 0x200, not MIO_HTML_MASK & 0x400) #filter_fields=True
#output_gpio_out(registers,f,MIO_HTML_MASK) #prohibited by RBL #output_gpio_out(registers,f,MIO_HTML_MASK) #prohibited by RBL
......
...@@ -81,7 +81,154 @@ CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0#0x30000 # number of bytes to load to the ...@@ -81,7 +81,154 @@ CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0#0x30000 # number of bytes to load to the
CONFIG_EZYNQ_START_EXEC= 0x00 # start of execution address CONFIG_EZYNQ_START_EXEC= 0x00 # start of execution address
CONFIG_EZYNQ_DDR_PERIPHERAL_CLKSRC = DDR PLL
CONFIG_EZYNQ_DDR_RAM_BASEADDR = 0x00100000
CONFIG_EZYNQ_DDR_RAM_HIGHADDR = 0x3FFFFFFF
CONFIG_EZYNQ_DDR_TARGET_FREQ_MHZ = 533.3333 # New added
CONFIG_EZYNQ_DDR_FREQ_MHZ = 533.333374 # Taking available CLK and divisors into account?
CONFIG_EZYNQ_DCI_PERIPHERAL_FREQMHZ = 10.158731 # Taking available CLK and divisors into account?
CONFIG_EZYNQ_DDR_ENABLE = 1
CONFIG_EZYNQ_DDR_MEMORY_TYPE = DDR3
CONFIG_EZYNQ_DDR_ECC = Disabled
CONFIG_EZYNQ_DDR_BUS_WIDTH = 32
CONFIG_EZYNQ_DDR_BL = 8
CONFIG_EZYNQ_DDR_HIGH_TEMP = False # Normal
CONFIG_EZYNQ_DDR_T_REFI_US = 7.8
CONFIG_EZYNQ_DDR_T_RFC = 300 # 350.0
CONFIG_EZYNQ_DDR_T_WR = 15.0 # Write recovery time
CONFIG_EZYNQ_DDR_RTP = 4
CONFIG_EZYNQ_DDR_T_RTP = 7.5
CONFIG_EZYNQ_DDR_WTR = 4
CONFIG_EZYNQ_DDR_T_WTR = 7.5
CONFIG_EZYNQ_DDR_XP = 4 # power down (DLL on) to any operation, cycles
CONFIG_EZYNQ_DDR_T_DQSCK_MAX = 5.5 # (LPDDR2 only)
CONFIG_EZYNQ_DDR_PARTNO = MT41K256M16RE-125
CONFIG_EZYNQ_DDR_DRAM_WIDTH = 16
#CONFIG_EZYNQ_DDR_DEVICE_CAPACITY_MBITS = 4096 - can be calculated
CONFIG_EZYNQ_DDR_SPEED_BIN = DDR3_1066F
CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL = 0
CONFIG_EZYNQ_DDR_TRAIN_READ_GATE = 0
CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE = 0
CONFIG_EZYNQ_DDR_CLOCK_STOP_EN = 0
CONFIG_EZYNQ_DDR_USE_INTERNAL_VREF = 0
# undisclosed algorithm, get values from ps7*
CONFIG_EZYNQ_DDR_OUT_SLEW_NEG = 26
CONFIG_EZYNQ_DDR_OUT_SLEW_POS = 26
CONFIG_EZYNQ_DDR_OUT_DRIVE_NEG = 12
CONFIG_EZYNQ_DDR_OUT_DRIVE_POS = 28
CONFIG_EZYNQ_DDR_BIDIR_SLEW_NEG = 31
CONFIG_EZYNQ_DDR_BIDIR_SLEW_POS = 6
CONFIG_EZYNQ_DDR_BIDIR_DRIVE_NEG = 12
CONFIG_EZYNQ_DDR_BIDIR_DRIVE_POS = 28
CONFIG_EZYNQ_DDR_FREQ_MHZ = 533.333333
CONFIG_EZYNQ_DDR_BANK_ADDR_COUNT = 3
CONFIG_EZYNQ_DDR_ROW_ADDR_COUNT = 15
CONFIG_EZYNQ_DDR_COL_ADDR_COUNT = 10
CONFIG_EZYNQ_DDR_CL = 7
CONFIG_EZYNQ_DDR_CWL = 6
#CONFIG_EZYNQ_DDR_T_RCD = 7
#CONFIG_EZYNQ_DDR_T_RP = 7
CONFIG_EZYNQ_DDR_RCD = 7
CONFIG_EZYNQ_DDR_RP = 7
CONFIG_EZYNQ_DDR_T_RC = 48.75
CONFIG_EZYNQ_DDR_T_RAS_MIN = 35.0
CONFIG_EZYNQ_DDR_T_FAW = 40.0
CONFIG_EZYNQ_DDR_AL = 0
CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0 = 0.0
CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1 = 0.0
CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2 = 0.0
CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3 = 0.0
CONFIG_EZYNQ_DDR_BOARD_DELAY0 = 0.0
CONFIG_EZYNQ_DDR_BOARD_DELAY1 = 0.0
CONFIG_EZYNQ_DDR_BOARD_DELAY2 = 0.0
CONFIG_EZYNQ_DDR_BOARD_DELAY3 = 0.0
CONFIG_EZYNQ_DDR_DQS_0_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQS_1_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQS_2_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQS_3_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQ_0_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQ_1_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQ_2_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQ_3_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_CLOCK_0_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_CLOCK_1_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_CLOCK_2_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_CLOCK_3_LENGTH_MM = 0
CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH = 504
CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH = 495
CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH = 520
CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH = 835
CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH = 465
CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH = 480
CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH = 550
CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH = 780
CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH = 470.0
CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH = 470.0
CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH = 470.0
CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH = 470.0
CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY = 160
CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY = 160
# PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 = -0.005
# PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 = -0.004
# PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 = -0.008
# PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 = -0.058
# PCW_PACKAGE_DDR_BOARD_DELAY0 = 0.075
# PCW_PACKAGE_DDR_BOARD_DELAY1 = 0.076
# PCW_PACKAGE_DDR_BOARD_DELAY2 = 0.082
# PCW_PACKAGE_DDR_BOARD_DELAY3 = 0.100
#just software testing - remove later
CONFIG_EZYNQ_DDR_SETREG_ctrl_reg1__reg_ddrc_selfref_en_PRE = 1
CONFIG_EZYNQ_DDR_SETREG_ctrl_reg1__reg_ddrc_lpr_num_entries_PRE = 5
CONFIG_EZYNQ_DDR_SETREG_phy_wr_dqs_cfg0_PRE = 0xAAAAA
CONFIG_EZYNQ_DDR_SETREG_phy_wr_dqs_cfg0__reg_phy_wr_dqs_slave_delay_PRE = 0x77
# 'reg_ddrc_selfref_en': {'r':(12,12),'d':0,'c':'Dynamic - 1 - go to Self Refresh when transaction store is empty'},
# 'reserved1': {'r':(11,11),'d':0,'m':'R','c':'reserved'},
# 'reg_ddrc_dis_collision_page_opt': {'r':(10,10),'d':0,'c':'Disable autoprecharge for collisions (write+write or read+write to the same address) when reg_ddrc_dis_wc==1'},
# 'reg_ddrc_dis_wc': {'r':( 9, 9),'d':0,'c':'1 - disable write combine, 0 - enable'},
# 'reg_ddrc_refresh_update_level': {'r':( 8, 8),'d':0,'c':'Dynamic: toggle to indicate refressh register(s) update'},
# 'reg_ddrc_auto_pre_en': {'r':( 7, 7),'d':0,'c':'1 - most R/W will be with autoprecharge'},
# 'reg_ddrc_lpr_num_entries': {'r':( 1, 6),'d':0x1F,'c':'(bit 6 ignored) (Size of low priority transaction store+1). HPR - 32 - this value'},
# 'reg_ddrc_pageclose': {'r':( 0, 0),'d':0,'c':'1 - close bank if no transactions in the store for it, 0 - keep open until not needed by other'}}},
# 'phy_wr_dqs_cfg0': {'OFFS': 0x154,'DFLT':0x00000000,'RW':'RW','FIELDS':{
# 'reg_phy_wr_dqs_slave_delay': {'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0'},
# 'reg_phy_wr_dqs_slave_force': {'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0'},
# 'reg_phy_wr_dqs_slave_ratio': {'r':( 0, 9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio'}}},
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