updating configuration for the microzed board

u-boot-tree/include/configs/ezynq/ezynq393.h

@@ -70,10 +70,8 @@
 
 #define CONFIG_EZYNQ_MIO_ETH_0__SLOW
 #define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW
-
 #define CONFIG_EZYNQ_MIO_USB_0__SLOW
 #define CONFIG_EZYNQ_MIO_USB_0__PULLUP
-
 #define CONFIG_EZYNQ_MIO_SDIO_0           40  /* 16,28,40 */
 #define CONFIG_EZYNQ_MIO_SDIO_0__SLOW
 #define CONFIG_EZYNQ_MIO_SDIO_0__PULLUP
@@ -192,8 +190,6 @@ output (or undefined) -   off
 
 #define CONFIG_EZYNQ_CLK_COMPLIANCE_PERCENT    5.0 /*  Allow exceeding maximal limits by this margin (percent */
 
-
-
 /*       Board PCB layout parameters (not yet used)      */
 #define CONFIG_EZYNQ_DDR_BOARD_DELAY0      0.0
 #define CONFIG_EZYNQ_DDR_BOARD_DELAY1      0.0
@@ -214,20 +210,6 @@ output (or undefined) -   off
 
 /* Below will overwrite calculated values (not yet calculated) */
 #if 1 /*testing old version */
-/* LED will be ON */
-//  #define CONFIG_EZYNQ_MIO_INOUT_53      OUT     /* Make output, do not set data. Will be set after debug will be over */
-
-
-/*  #define CONFIG_EZYNQ_MIO_GPIO_OUT_53     0 */    /* Set selected GPIO output to 0/1 */
-  #undef  CONFIG_EZYNQ_DDR_DS_CKE
-  #define CONFIG_EZYNQ_DDR_DS_CKE               4   /* CKE min pulse width (in tCK) */
-
-//  #undef  CONFIG_EZYNQ_DDR_DS_WLMRD
-//  #define CONFIG_EZYNQ_DDR_DS_WLMRD            22   /* Write leveling : time to the first DQS rising edge (cycles). */
-
-
-
-/*  #define CONFIG_EZYNQ_LED_DEBUG          53 */    /* toggle LED during boot - temporary, normal use - MDIO_D */
   #define CONFIG_EZYNQ_UART_DEBUG_USE_LED    N    /* turn on/off LED while waiting for transmit FIFO not full */
 
   #define CONFIG_EZYNQ_SILICON               3 /* 3 */        /* Silicon revision */
@@ -262,7 +244,7 @@ output (or undefined) -   off
   #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 3 */
 
   #define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x80     /* Ratio for address/command (256 - clock period) */
-  #define CONFIG_EZYNQ_PHY_INVERT_CLK             N     /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
+  #define CONFIG_EZYNQ_PHY_INVERT_CLK             N     /* Invert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
 
 #else
   #define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW 
@@ -294,7 +276,7 @@ output (or undefined) -   off
   #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3 0xc7 /* Ratio for write data slave DLL (256 - clock period), slice 3 */
 
   #define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x100     /* Ratio for address/command (256 - clock period) */
-  #define CONFIG_EZYNQ_PHY_INVERT_CLK                     /* RInvert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
+  #define CONFIG_EZYNQ_PHY_INVERT_CLK                     /* Invert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
 
 #endif
 

u-boot-tree/include/configs/ezynq/zed_ezynq.h

@@ -17,6 +17,7 @@
 #define __CONFIG_EZYNQ_H
 #define CONFIG_EZYNQ
 
+
 /* Boot image cionfiguration parameters */
 
 #define CONFIG_EZYNQ_BOOT_USERDEF           0x1010000 /*  0x1234567  will be saved in the file header */
@@ -26,18 +27,29 @@
 #define CONFIG_EZYNQ_RESERVED44             0         /*   documented as 0, but actually 1 */
 
 /* Boot debug setup */
-#define CONFIG_EZYNQ_BOOT_DEBUG            /* configure UARTx and send register dumps there.*/
+#define CONFIG_EZYNQ_BOOT_DEBUG        Y   /* configure UARTx and send register dumps there.*/
 #define CONFIG_EZYNQ_LOCK_SLCR         OFF /* Lock SLCR registers when all is done. */
 #define CONFIG_EZYNQ_LED_DEBUG          47 /* toggle LED during boot */
 #define CONFIG_EZYNQ_UART_DEBUG_USE_LED    /* turn on/off LED while waiting for transmit FIFO not full */
 
-#define CONFIG_EZYNQ_DUMP_SLCR_EARLY       /* Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
-#define CONFIG_EZYNQ_DUMP_DDRC_EARLY       /* Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
-#define CONFIG_EZYNQ_DUMP_SLCR_LATE        /* Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
-#define CONFIG_EZYNQ_DUMP_DDRC_LATE        /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
+#define CONFIG_EZYNQ_DUMP_SLCR_EARLY     N /* Dump SLCR registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
+#define CONFIG_EZYNQ_DUMP_DDRC_EARLY     N /* Dump DDRC registers as soon as UART is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
+#define CONFIG_EZYNQ_DUMP_SLCR_LATE      N /* Dump SLCR registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
+#define CONFIG_EZYNQ_DUMP_DDRC_LATE      N  /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
+#define CONFIG_EZYNQ_DUMP_TRAINING_EARLY N /* Training results registers before DDRC initialization */
+#define CONFIG_EZYNQ_DUMP_TRAINING_LATE  Y /* Training results registers after DDRC initialization */
+#define CONFIG_EZYNQ_DUMP_OCM            y /* Dump (some of) OCM data */
+#define CONFIG_EZYNQ_DUMP_DDR            y  /* Dump (some of) DDR data */
+#if 1
+#define CONFIG_EZYNQ_DUMP_OCM_LOW        0x0   /* OCM dump start (deafault 0)     */
+#define CONFIG_EZYNQ_DUMP_OCM_HIGH     0x2ff   /* OCM dump end   (deafault 0x2ff, full - 0x2ffff) */
+
+#define CONFIG_EZYNQ_DUMP_DDR_LOW  0x4000000  /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
+#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff  /* DDR dump end   (deafault 0x40002ff) */
+#endif
 /* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
    If defined, each can be 0,1, ON or OFF */
-#define CONFIG_EZYNQ_LED_CHECKPOINT_1   ON  /* in RBL setup, as soon as MIO is programmed */
+#define CONFIG_EZYNQ_LED_CHECKPOINT_1   OFF /* in RBL setup, as soon as MIO is programmed, should be OFF to use GPIO */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_2   OFF /* First after getting to user code */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_3   ON  /* After setting clock registers */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_4   OFF /* After PLL bypass is OFF */
@@ -49,6 +61,7 @@
 #define CONFIG_EZYNQ_LED_CHECKPOINT_10  OFF /* Before remapping OCM0-OCM2 high */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_11  ON  /* After remapping OCM0-OCM2 high */
 #define CONFIG_EZYNQ_LED_CHECKPOINT_12  OFF /* Before leaving lowlevel_init() */
+#define CONFIG_EZYNQ_LAST_PRINT_DEBUG   y   /* 'Output to UART before exiting arch_cpu_init() */ 
 /* MIO configuration */
 #define CONFIG_EZYNQ_OCM                         /* not used */
 #define CONFIG_EZYNQ_MIO_0_VOLT           3.3
@@ -61,6 +74,12 @@
 #define CONFIG_EZYNQ_MIO_SDIO_0           40  /* 16,28,40 */
 #define CONFIG_EZYNQ_MIO_SDIO_0__SLOW
 #define CONFIG_EZYNQ_MIO_SDIO_0__PULLUP
+#define CONFIG_EZYNQ_MIO_SDIO_0           40  /* 16,28,40 */
+#define CONFIG_EZYNQ_MIO_SDIO_0__SLOW
+#define CONFIG_EZYNQ_MIO_SDIO_0__PULLUP
+#define CONFIG_EZYNQ_MIO_SDIO_0           40  /* 16,28,40 */
+#define CONFIG_EZYNQ_MIO_SDIO_0__SLOW
+#define CONFIG_EZYNQ_MIO_SDIO_0__PULLUP
 #define CONFIG_EZYNQ_MIO_SDCD_0           46  /* any but 7,8  */
 #define CONFIG_EZYNQ_MIO_SDCD_0__PULLUP
 #define CONFIG_EZYNQ_MIO_SDWP_0           50  /* #any but 7,8  */
@@ -72,15 +91,10 @@
 
 /*
 Red LED - pullup, input - on,
-output (or undefined) -   off
-#define CONFIG_EZYNQ_MIO_PULLUP_EN_47
-#define CONFIG_EZYNQ_MIO_PULLUP_DIS_0
 #define CONFIG_EZYNQ_MIO_INOUT_47   OUT
 #define CONFIG_EZYNQ_MIO_INOUT_47   IN
 #define CONFIG_EZYNQ_MIO_INOUT_47   BIDIR
 */
-
-/*       DDR chip independent      */
 #define CONFIG_EZYNQ_DDR_ENABLE             Y        /*  Enable DDR memory */
 /* Only specify CONFIG_EZYNQ_DDR_FREQ_MHZ if you want the DDR frequency used for timing calculations is different from actual */
 /* #define CONFIG_EZYNQ_DDR_FREQ_MHZ    533.333333 */ /*  DDR clock frequency in MHz, this value overwrites the one calculated by the PLL/clock setup */
@@ -174,8 +188,6 @@ output (or undefined) -   off
 
 #define CONFIG_EZYNQ_CLK_COMPLIANCE_PERCENT    5.0 /*  Allow exceeding maximal limits by this margin (percent */
 
-
-
 /*       Board PCB layout parameters (not yet used)      */
 #define CONFIG_EZYNQ_DDR_BOARD_DELAY0      0.0
 #define CONFIG_EZYNQ_DDR_BOARD_DELAY1      0.0
@@ -198,6 +210,42 @@ output (or undefined) -   off
 #define CONFIG_EZYNQ_DDR_RAM_BASEADDR   0x00100000
 #define CONFIG_EZYNQ_DDR_RAM_HIGHADDR   0x3FFFFFFF
 */
-
+/* Below will overwrite calculated values (not yet calculated) */
+  #define CONFIG_EZYNQ_SILICON               3 /* 3 */        /* Silicon revision */
+  #define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_0 0x0 /* Initial ratio for write leveling FSM, slice 0 */
+  #define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_1 0x0 /* Initial ratio for write leveling FSM, slice 1 */
+  #define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_2 0x0 /* Initial ratio for write leveling FSM, slice 2 */
+  #define CONFIG_EZYNQ_PHY_WRLV_INIT_RATIO_3 0x0 /* Initial ratio for write leveling FSM, slice 3 */
+
+  #define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_0 0x0 /* Initial ratio for gate leveling FSM, slice 0 */
+  #define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_1 0x0 /* Initial ratio for gate leveling FSM, slice 1 */
+  #define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_2 0x0 /* Initial ratio for gate leveling FSM, slice 2 */
+  #define CONFIG_EZYNQ_PHY_GTLV_INIT_RATIO_3 0x0 /* Initial ratio for gate leveling FSM, slice 3 */
+
+  #define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_0 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_1 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 1 */
+  #define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_2 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 2 */
+  #define CONFIG_EZYNQ_PHY_RD_DQS_SLAVE_RATIO_3 0x35/* Ratio for read DQS slave DLL (256 - clock period), slice 3 */
+
+  #define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_0 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_1 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 1 */
+  #define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_2 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 2 */
+  #define CONFIG_EZYNQ_PHY_WR_DQS_SLAVE_RATIO_3 0x0 /* Ratio for write DQS slave DLL (256 - clock period), slice 3 */
+
+  #define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_0 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_1 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_2 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_FIFO_WE_SLAVE_RATIO_3 0x35 /*Ratio for FIFO WE slave DLL (256 - clock period), slice 0 */
+
+  #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_0 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 0 */
+  #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_1 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 1 */
+  #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_2 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 2 */
+  #define CONFIG_EZYNQ_PHY_PHY_WR_DATA_SLAVE_RATIO_3 0x40 /* Ratio for write data slave DLL (256 - clock period), slice 3 */
+
+  #define CONFIG_EZYNQ_PHY_PHY_CTRL_SLAVE_RATIO 0x80     /* Ratio for address/command (256 - clock period) */
+  #define CONFIG_EZYNQ_PHY_INVERT_CLK             N     /* Invert CLK out (if clk can arrive to DRAM chip earlier/at the same time as DQS) */
+
+ 
+ 
 
 #endif /* __CONFIG_EZYNQ_H */

u-boot-tree/include/configs/zynq_microzed.h

@@ -30,17 +30,19 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_ZYNQ_SDHCI0
-//#define CONFIG_ZYNQ_SPI
+/* #define CONFIG_ZYNQ_SPI */
 
-//#define CONFIG_NAND_ZYNQ
+/* #define CONFIG_NAND_ZYNQ */
 #undef CONFIG_SYS_TEXT_BASE
 #include <configs/zynq_common.h>
 #include <configs/ezynq/ezynq_MT41K256M16RE125.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
 #include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
 #include <configs/ezynq/zed_ezynq.h>
 
-//#define CONFIG_CMD_MEMTEST
-#undef CONFIG_EZYNQ_BOOT_DEBUG 
+#if 1
+  #undef CONFIG_EZYNQ_BOOT_DEBUG        Y    /* configure UARTx and send register dumps there.*/
+#endif
+#define CONFIG_CMD_MEMTEST
 
 /* twice slower */
 #undef CONFIG_ZYNQ_SERIAL_CLOCK0
@@ -66,14 +68,14 @@
 #if 0
   #define CONFIG_SYS_TEXT_BASE		0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */
 #else
-  #define CONFIG_SYS_TEXT_BASE		0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
+#define CONFIG_SYS_TEXT_BASE		0x00000000
 #endif
 /*
 #define CONFIG_EZYNQ_SKIP_DDR
 */
 #define CONFIG_EZYNQ_SKIP_CLK
 
-//undefs
+/* undefs */
 
 /* undefs */
 /*#undef CONFIG_FS_FAT */