Moved ezynq-specific initialization from lowlevel_init() to arch_cpu_init(),... (8a9be5dd) · Commits · Elphel / ezynq

ezynq_uboot.py

+8 −7

Original line number	Original line	Diff line number	Diff line
	@@ -162,14 +162,14 @@ class EzynqUBoot:
	self.sections.append('slcr_lock_unlock_setup')		self.sections.append('slcr_lock_unlock_setup')
	self.cfile+="""		self.cfile+="""
	/* Lock SLCR registers - may be called after everything is done. */		/* Lock SLCR registers - may be called after everything is done. */
	void lock_slcr(void)		inline void lock_slcr(void)
	{		{
	"""		"""
	self._add_reg_writes(reg_sets[:1])		self._add_reg_writes(reg_sets[:1])
	self.cfile+="""}		self.cfile+="""}

	/* Unlock SLCR registers - SHOULD be called first before writing any SLCR registers. */		/* Unlock SLCR registers - SHOULD be called first before writing any SLCR registers. */
	void unlock_slcr(void)		inline void unlock_slcr(void)
	{		{
	"""		"""
	self._add_reg_writes(reg_sets[1:])		self._add_reg_writes(reg_sets[1:])
	@@ -237,7 +237,7 @@ inline void uart_init(void)
	comments=''		comments=''
	self.cfile+='''/* Wait FIFO is empty (call before getting to risky for reboot code		self.cfile+='''/* Wait FIFO is empty (call before getting to risky for reboot code
	to make sure all output has been actually sent */		to make sure all output has been actually sent */
	void uart_wait_tx_fifo_empty(void)		inline void uart_wait_tx_fifo_empty(void)
	{		{
	'''		'''
	self._add_reg_writes([reg_sets[0]])		self._add_reg_writes([reg_sets[0]])
	@@ -387,11 +387,11 @@ inline void ddrc_wait_queue_empty(void)
	else:		else:
	self.cfile+='\tdebug_led_off(); /* Turn debug LED OFF */\n'		self.cfile+='\tdebug_led_off(); /* Turn debug LED OFF */\n'

	def make_lowlevel_init (self):		def make_arch_cpu_init (self):


	self.cfile+='''/* Initialize clocks, DDR memory, copy OCM to DDR */		self.cfile+='''/* Initialize clocks, DDR memory, copy OCM to DDR */
	void lowlevel_init(void)		int arch_cpu_init(void)
	{		{
	/* Unlock SLCR */		/* Unlock SLCR */
	\tunlock_slcr();		\tunlock_slcr();
	@@ -518,19 +518,20 @@ void lowlevel_init(void)
	self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init()		self._cp_led('LED_CHECKPOINT_12') # Before leaving lowlevel_init()
	#LOCK_SLCR		#LOCK_SLCR
	if self.features.get_par_value_or_none('LOCK_SLCR') is False:		if self.features.get_par_value_or_none('LOCK_SLCR') is False:
	self.cfile+='/* Leaving SLCR registers UNLOCKED */\n'		self.cfile+='/* Leaving SLCR registers UNLOCKED according setting of %s */\n'%self.features.get_par_confname('LOCK_SLCR')
	else:		else:
	self.cfile+='''/* Lock SLCR back after everything with it is done */		self.cfile+='''/* Lock SLCR back after everything with it is done */
	\tlock_slcr();		\tlock_slcr();
	'''		'''
	self.cfile+='''/* This code was called from low OCM, so return should just get back correctly */		self.cfile+='''/* This code was called from low OCM, so return should just get back correctly */
			\treturn 0;
	}		}
	'''		'''

	def output_c_file(self,cname):		def output_c_file(self,cname):
	if not cname:		if not cname:
	return		return
	print 'Writing generated u-boot lowlevel() function to ',os.path.abspath(cname)		print 'Writing generated u-boot arch_cpu_init() function to ',os.path.abspath(cname)
	c_out_file=open(cname,'w')		c_out_file=open(cname,'w')
	c_out_file.write(self.cfile)		c_out_file.write(self.cfile)
	c_out_file.close()		c_out_file.close()

ezynqcfg.py

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -523,6 +523,6 @@ if (args.lowlevel):
	if 'DDRC_STA' in segment_dict:		if 'DDRC_STA' in segment_dict:
	u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']])		u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']])

	u_boot.make_lowlevel_init()		u_boot.make_arch_cpu_init()
	u_boot.output_c_file(args.lowlevel)		u_boot.output_c_file(args.lowlevel)
	# print u_boot.get_c_file()		# print u_boot.get_c_file()

u-boot-tree/arch/arm/cpu/armv7/zynq/Makefile

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -33,7 +33,7 @@ COBJS-y += cpu.o
	COBJS-y += ddrc.o		COBJS-y += ddrc.o
	COBJS-y += slcr.o		COBJS-y += slcr.o
	ifneq ($(CONFIG_EZYNQ),)		ifneq ($(CONFIG_EZYNQ),)
	COBJS-y += lowlevel.o		COBJS-y += ezynq.o
	endif		endif

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