inactiveToPDx32=6# cycles 'Power down after this many clocks of NOP/DESELECT (if enabled in mcr). Make configurable?
WR=int(math.ceil(tWR/tCK))
# print 'tWR=',tWR,'tCK=',tCK
wr_options_ddr3=(16,5,6,7,8,10,12,14)
# some values are not valid for DDR3 when writing to MR0 register, trying to fix WR (in tCK) to be valid
ifis_DDR3and(notWRinwr_options_ddr3):
print'Calculated value for Write recovery (WR): '+str(WR)+' (as defined by tWR), is not valid for DDR3 MR0, it only supports '+str(sorted(wr_options_ddr3))
print'trying to adjust WR:'
cheat_down=0.1# reduce calculated WR if before rounding up it did not exceed integer value by more than 'cheat'
WR1=int(math.ceil(tWR/tCK-cheat_down))
ifWR1inwr_options_ddr3:
print'Using WR='+str(WR1)+' instead of '+str(WR)+' (cheating down), before rounding the value was '+str(tWR/tCK)
WR=WR1
elif(WR+1)inwr_options_ddr3:
print'Using WR='+str(WR+1)+' instead of '+str(WR)+' (to much to cheat down, increasing to next valid), before rounding the value was '+str(tWR/tCK)
WR=WR+1
else:
raiseException('Could not fix the value of WR, please check frequency ('+self.features.get_par_confname('FREQ_MHZ')+
') and write recovery (ns) '+self.features.get_par_confname('T_WR'))
WL=self.features.get_par_value('CWL')
BL=self.features.get_par_value('BL')
wr2pre=WL+BL/2+WR
...
...
@@ -515,11 +534,11 @@ class EzynqDDR:
except:
raiseException('Wrong value for CAS latency: '+str(CL)+' - only CL=5..14 are supported by DDR3')
mr_dll_reset=1# Seems to be always set (including dflt)?
wr_options=(16,5,6,7,8,10,12,14)
wr_options_ddr3=(16,5,6,7,8,10,12,14)
try:
mr_write_recovery=wr_options.index(WR)
mr_write_recovery=wr_options_ddr3.index(WR)
except:
raiseException('Wrong value for Write recovery (WR): '+str(WR)+' (may be defined by tWR), DDR3 only supports '+str(wr_options))
raiseException('Wrong value for Write recovery (WR): '+str(WR)+' (may be defined by tWR), DDR3 only supports '+str(sorted(wr_options_ddr3)))
mr_PD=0# 0 - DLL off during PD (slow exit), 1 - DLL on during PD (fast exit)
#CONFIG_EZYNQ_DDR_ARB_PAGE_BANK = N # Y # default N, testing
CONFIG_EZYNQ_DDR_CL = 7
CONFIG_EZYNQ_DDR_CWL = 6
#CONFIG_EZYNQ_DDR_T_RCD = 7
#CONFIG_EZYNQ_DDR_T_RP = 7
#testing calculation of derivative parameters
#CONFIG_EZYNQ_DDR_RCD = 7
#CONFIG_EZYNQ_DDR_RP = 7
CONFIG_EZYNQ_DDR_T_RP = 13.1
CONFIG_EZYNQ_DDR_T_RCD = 13.1
CONFIG_EZYNQ_DDR_CCD = 5 # 4 in Micron specs
#will use max of two
CONFIG_EZYNQ_DDR_RRD = 6 # 4 in Micron specs
CONFIG_EZYNQ_DDR_T_RRD = 10.0
CONFIG_EZYNQ_DDR_MRD = 4
CONFIG_EZYNQ_DDR2_RTT = 75 # DISABLED, 75,150,50 - only used for DDR2
CONFIG_EZYNQ_DDR3_RTT = 60 # DISABLED, 60,120,40 - only used for DDR3
CONFIG_EZYNQ_DDR_T_RC = 48.75
CONFIG_EZYNQ_DDR_T_RAS_MIN = 35.0
CONFIG_EZYNQ_DDR_T_FAW = 40.0
CONFIG_EZYNQ_DDR_AL = 0
# not yet processed
CONFIG_EZYNQ_DCI_PERIPHERAL_FREQMHZ = 10.158731 # Taking available CLK and divisors into account?
CONFIG_EZYNQ_DDR_PERIPHERAL_CLKSRC = DDR PLL
CONFIG_EZYNQ_DDR_RAM_BASEADDR = 0x00100000
CONFIG_EZYNQ_DDR_RAM_HIGHADDR = 0x3FFFFFFF
##### DDR independent ######
CONFIG_EZYNQ_DDR_ENABLE = Y # Enable DDR memory'},
CONFIG_EZYNQ_DDR_TARGET_FREQ_MHZ = 533.3333 # Target DDR clock frequency in MHz (actual frequency will depend on the clock/clock muxes)
#CONFIG_EZYNQ_DDR_FREQ_MHZ = 545.0 # Actual DDR clock frequency in MHz, may be derived form CONFIG_EZYNQ_DDR_TARGET_FREQ_MHZ and clock multiplexer settings. Causes tWR to go higher
#CONFIG_EZYNQ_DDR_FREQ_MHZ = 533.333374 # Actual DDR clock frequency in MHz, may be derived form CONFIG_EZYNQ_DDR_TARGET_FREQ_MHZ and clock multiplexer settings. Causes tWR to go higher
CONFIG_EZYNQ_DDR_FREQ_MHZ = 533.3333 # Actual DDR clock frequency in MHz, may be derived form CONFIG_EZYNQ_DDR_TARGET_FREQ_MHZ and clock multiplexer settings
CONFIG_EZYNQ_DDR_BANK_ADDR_MAP = 10 # DRAM address mapping: number of combined column and row addresses lower than BA0
CONFIG_EZYNQ_DDR_ARB_PAGE_BANK = N # Enable Arbiter prioritization based on page/bank match
CONFIG_EZYNQ_DDR_ECC = Disabled # Enable ECC for the DDR memory
CONFIG_EZYNQ_DDR_BUS_WIDTH = 32 # SoC DDR bus width
CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL =0 # Automatically train write leveling during initialization
CONFIG_EZYNQ_DDR_DDR3_RTT = 60 # DDR3 on-chip termination, Ohm ('DISABLED','60','120','40')# Does not include 20 & 30 - not clear if DDRC can use them with auto write leveling
CONFIG_EZYNQ_DDR_DS_T_RFC = 300.0 # Minimal Refresh-to-Activate or Refresh command period (ns)
CONFIG_EZYNQ_DDR_DS_T_WR = 15.0 # Write recovery time (ns)
CONFIG_EZYNQ_DDR_DS_T_REFI_US = 7.8 # Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected
CONFIG_EZYNQ_DDR_DS_RTP = 4 # Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK
CONFIG_EZYNQ_DDR_DS_T_RTP = 7.5 # Minimal Read-to-Precharge time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP
CONFIG_EZYNQ_DDR_DS_WTR = 4 # Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK
CONFIG_EZYNQ_DDR_DS_T_WTR = 7.5 # Minimal Write-to-Read time (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR
CONFIG_EZYNQ_DDR_DS_XP = 4 # Minimal time from power down (DLL on) to any operation (in tCK)
CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX = 5.5 # LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2
CONFIG_EZYNQ_DDR_DS_CCD = 5 # DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS)
CONFIG_EZYNQ_DDR_DS_RRD = 6 # ACTIVATE-to-ACTIVATE minimal command period (in tCK)
CONFIG_EZYNQ_DDR_DS_T_RRD 10.0 # ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically
CONFIG_EZYNQ_DDR_DS_MRD = 4 # MODE REGISTER SET command period (in tCK)
CONFIG_EZYNQ_DDR_DS_MOD = 12 # MODE REGISTER SET update delay (in tCK)
CONFIG_EZYNQ_DDR_DS_T_MOD = 15.0 # MODE REGISTER SET update delay (ns).
CONFIG_EZYNQ_DDR_DS_T_WLMRD = 40.0 # Write leveling : time to the first DQS rising edge (ns).
CONFIG_EZYNQ_DDR_DS_CKE = 3 # CKE min pulse width (in tCK)
