fori,map_bitinenumerate(map_axi[3:]):# skip 3 LSB to get "This mask applies to 64-bit address and not byte address.". ***** TODO: Verify it is really 64 (8-byte), not 32 (4-byte) word address
ifmap_bit['TYPE']in'BR':
page_mask|=1<<i
#now validate mapping, raise exception if invalid
address_mapping={}
fornameinmap_capabilities:
...
...
@@ -240,25 +245,10 @@ class EzynqDDR:
else:
value=map_field(name,capability[1])
address_mapping[name]=value
returnaddress_mapping
# def set_max_value(self,name,value):
# def set_min_value(self,name,value):
# CONFIG_EZYNQ_DDR_T_RP = 13.1
# CONFIG_EZYNQ_DDR_T_RCD = 13.1
#CONFIG_EZYNQ_DDR_RRD = 4
#CONFIG_EZYNQ_DDR_T_RRD = 10.0
# def ddr_init_memory(self,current_reg_sets,force=False,warn=False,html_file, show_bit_fields=True, show_comments=True,filter_fields=True): # will program to sequence 'MAIN'
final_wait_x32=0x7# leaving default - time to start scheduler after dram init init
...
...
@@ -496,7 +447,7 @@ class EzynqDDR:
elifAL==(CL-2):
emr_AL=2
else:
raiseException("Wrong value for additive latency (CONFIG_EZYNQ_DDR_AL): "+str(AL)+", only 0, CL-1, CL-2 are supported in DDR3 memory. CL is "+str(CL))
raiseException('Wrong value for additive latency ('+self.features.get_par_confname('AL')+': '+str(AL)+', only 0, CL-1, CL-2 are supported in DDR3 memory. CL is '+str(CL))
# ddrc_register_set.set_bitfields('che_corr_ecc_data_63_32_reg_offset',(('corr_ecc_dat_63_32', 0)),force,warn) #0 bits[32:63] of the word with correctable ECC error. actually all are 0'
# ddrc_register_set.set_bitfields('che_corr_ecc_data_71_64_reg_offset',(('corr_ecc_dat_71_64', 0)),force,warn) #0 bits[64:71] of the word with correctable ECC error. only lower 5 bits have data, the rest are 0
# ddrc_register_set.set_bitfields('che_uncorr_ecc_log_reg_offset',(('uncorr_ecc_log_valid', 0)),force,warn) # Set to 1 when uncorrectable error is capture (no more captured until cleared), cleared by che_ecc_control_reg_offset
# ddrc_register_set.set_bitfields('uncorr_ecc_dat_31_0',(('reserved1', 0)),force,warn) # bits[0:31] of the word with uncorrectable ECC error. actually only 0:7 have valid data, 8:31 are 0
# ddrc_register_set.set_bitfields('che_uncorr_ecc_data_63_32_reg_offset',(('reserved1', 0)),force,warn) # bits[32:63] of the word with uncorrectable ECC error. actually all are 0
# ddrc_register_set.set_bitfields('che_uncorr_ecc_data_71_64_reg_offset',(('reserved1', 0)),force,warn) # bits[64:71] of the word with uncorrectable ECC error. only lower 5 bits have data, the rest are 0
# reg che_ecc_stats_reg_offset (offset=0xf0): Clear on write
# 'stat_num_corr_err': {'r':( 8,15),'d':0,'m':'R','c':'Number of correctable ECC errors since 1 written to bit 1 of che_ecc_control_reg_offset (0xC4)'},
# 'stat_num_uncorr_err': {'r':( 0, 7),'d':0,'m':'R','c':'Number of uncorrectable ECC errors since 1 written to bit 0 of che_ecc_control_reg_offset (0xC4)'}}},
# ddrc_register_set.set_bitfields('che_ecc_corr_bit_mask_31_0_reg_offset',(('ddrc_reg_ecc_corr_bit_mask', 0)),force,warn) # bits[0:31] of the mask of the corrected data (1 - corrected, 0 - uncorrected). Only 0:7 have valid data, 8:31 are 0
# ddrc_register_set.set_bitfields('che_ecc_corr_bit_mask_63_32_reg_offset',(('ddrc_reg_ecc_corr_bit_mask', 0)),force,warn) #bits[32:63] of the mask of the corrected data (1 - corrected, 0 - uncorrected). all bits are 0
# end of if useECC:
# reg ecc_scrub, offs=0x0F4 dflt:0x8 actual:0x8 (apply even with ECC disabled?)
ddrc_register_set.set_bitfields('phy_config0',(# PHY configuration for data slice 0
('reg_phy_dq_offset',0x40),# 0x40 Offset value of DQS to DQ during write leveling of data slice 0. Default is 0x40 for 90-degree shift
('reg_phy_bist_err_clr',0),#
('reg_phy_bist_shift_dq',0),#
('reg_phy_board_lpbk_rx',0),#
('reg_phy_board_lpbk_tx',0),#
('reg_phy_wrlvl_inc_mode',0),#
('reg_phy_gatelvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_data_slice_in_use',slice_in_use0),# 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 0 is valid (always 1)
ddrc_register_set.set_bitfields('phy_config1',(# PHY configuration for data slice 0
('reg_phy_dq_offset',0x40),# 0x40 Offset value of DQS to DQ during write leveling of data slice 1. Default is 0x40 for 90-degree shift
('reg_phy_bist_err_clr',0),#
('reg_phy_bist_shift_dq',0),#
('reg_phy_board_lpbk_rx',0),#
('reg_phy_board_lpbk_tx',0),#
('reg_phy_wrlvl_inc_mode',0),#
('reg_phy_gatelvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_data_slice_in_use',slice_in_use1),# 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 1 is valid (always 1)
ddrc_register_set.set_bitfields('phy_config2',(# PHY configuration for data slice 0
('reg_phy_dq_offset',0x40),# 0x40 Offset value of DQS to DQ during write leveling of data slice 2. Default is 0x40 for 90-degree shift
('reg_phy_bist_err_clr',0),#
('reg_phy_bist_shift_dq',0),#
('reg_phy_board_lpbk_rx',0),#
('reg_phy_board_lpbk_tx',0),#
('reg_phy_wrlvl_inc_mode',0),#
('reg_phy_gatelvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_data_slice_in_use',slice_in_use2),# 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 2 is valid (always 1)
ddrc_register_set.set_bitfields('phy_config3',(# PHY configuration for data slice 0
('reg_phy_dq_offset',0x40),# 0x40 Offset value of DQS to DQ during write leveling of data slice 3. Default is 0x40 for 90-degree shift
('reg_phy_bist_err_clr',0),#
('reg_phy_bist_shift_dq',0),#
('reg_phy_board_lpbk_rx',0),#
('reg_phy_board_lpbk_tx',0),#
('reg_phy_wrlvl_inc_mode',0),#
('reg_phy_gatelvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_rdlvl_inc_mode',0),#
('reg_phy_data_slice_in_use',slice_in_use3),# 1 Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 3 is valid (always 1)
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg0',(# PHY read DQS configuration register for data slice 0
('reg_phy_rd_dqs_slave_delay',0),# 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 0
('reg_phy_rd_dqs_slave_force',0),# 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 0
('reg_phy_rd_dqs_slave_ratio',dqs_slave_ratio0),# 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg1',(# PHY read DQS configuration register for data slice 1
('reg_phy_rd_dqs_slave_delay',0),# 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 1
('reg_phy_rd_dqs_slave_force',0),# 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 1
('reg_phy_rd_dqs_slave_ratio',dqs_slave_ratio1),# 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg2',(# PHY read DQS configuration register for data slice 2
('reg_phy_rd_dqs_slave_delay',0),# 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 2
('reg_phy_rd_dqs_slave_force',0),# 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 2
('reg_phy_rd_dqs_slave_ratio',dqs_slave_ratio2),# 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2
ddrc_register_set.set_bitfields('phy_rd_dqs_cfg3',(# PHY read DQS configuration register for data slice 3
('reg_phy_rd_dqs_slave_delay',0),# 0 If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 3
('reg_phy_rd_dqs_slave_force',0),# 0 0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 3
('reg_phy_rd_dqs_slave_ratio',dqs_slave_ratio3),# 0x35 Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg0',(# ,PHY write DQS configuration register for data slice 0
('reg_phy_wr_dqs_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0
('reg_phy_wr_dqs_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0
('reg_phy_wr_dqs_slave_ratio',0),# 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg1',(# ,PHY write DQS configuration register for data slice 1
('reg_phy_wr_dqs_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 1
('reg_phy_wr_dqs_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1
('reg_phy_wr_dqs_slave_ratio',0),# 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg2',(# ,PHY write DQS configuration register for data slice 2
('reg_phy_wr_dqs_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 2
('reg_phy_wr_dqs_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2
('reg_phy_wr_dqs_slave_ratio',0),# 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio
ddrc_register_set.set_bitfields('phy_wr_dqs_cfg3',(# ,PHY write DQS configuration register for data slice 3
('reg_phy_wr_dqs_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 3
('reg_phy_wr_dqs_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3
('reg_phy_wr_dqs_slave_ratio',0),# 0 Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio
ddrc_register_set.set_bitfields('phy_we_cfg0',(# PHY FIFO write enable configuration register for data slice 0
('reg_phy_fifo_we_in_delay',0),# 0 If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_0 slave DLL, data slice 0
('reg_phy_fifo_we_in_force',0),# 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 0
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio0),# 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 0. Program manual training ratio
ddrc_register_set.set_bitfields('phy_we_cfg1',(# PHY FIFO write enable configuration register for data slice 1
('reg_phy_fifo_we_in_delay',0),# 0 If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_0 slave DLL, data slice 1
('reg_phy_fifo_we_in_force',0),# 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 1
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio1),# 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 1. Program manual training ratio
ddrc_register_set.set_bitfields('phy_we_cfg2',(# PHY FIFO write enable configuration register for data slice 2
('reg_phy_fifo_we_in_delay',0),# 0 If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_0 slave DLL, data slice 2
('reg_phy_fifo_we_in_force',0),# 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 2
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio2),# 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 2. Program manual training ratio
ddrc_register_set.set_bitfields('phy_we_cfg3',(# PHY FIFO write enable configuration register for data slice 3
('reg_phy_fifo_we_in_delay',0),# 0 If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_0 slave DLL, data slice 3
('reg_phy_fifo_we_in_force',0),# 0 0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 3
('reg_phy_fifo_we_slave_ratio',fifo_we_slave_ratio3),# 0x35 Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 3. Program manual training ratio
ddrc_register_set.set_bitfields('wr_data_slv0',(# PHY write data slave ratio configuration register for data slice 0
('reg_phy_wr_data_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 0
('reg_phy_wr_data_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio0),# 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 0. Program manual training ratio
ddrc_register_set.set_bitfields('wr_data_slv1',(# PHY write data slave ratio configuration register for data slice 1
('reg_phy_wr_data_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 1
('reg_phy_wr_data_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio1),# 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 1. Program manual training ratio
ddrc_register_set.set_bitfields('wr_data_slv2',(# PHY write data slave ratio configuration register for data slice 2
('reg_phy_wr_data_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 2
('reg_phy_wr_data_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio2),# 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 2. Program manual training ratio
ddrc_register_set.set_bitfields('wr_data_slv3',(# PHY write data slave ratio configuration register for data slice 3
('reg_phy_wr_data_slave_delay',0),# 0 If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 3
('reg_phy_wr_data_slave_force',0),# 0 0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3
('reg_phy_wr_data_slave_ratio',wr_data_slave_ratio3),# 0x40 Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 3. Program manual training ratio
# def parse_options_set(self,raw_configs,prefix,postfix,qualifier_char,force=True,warn=True): #force - readonly/undefined fields, warn: data does not fit in the bit field
'reg_phy_data_slice_in_use':{'r':(0,0),'d':1,'c':'Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 0 is valid (always 1)'}}},
'reg_phy_data_slice_in_use':{'r':(0,0),'d':1,'c':'Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 1 is valid'}}},
'reg_phy_data_slice_in_use':{'r':(0,0),'d':1,'c':'Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 2 is valid'}}},
'reg_phy_data_slice_in_use':{'r':(0,0),'d':1,'c':'Data bus width for read FIFO generation. 0 - read data responses are ignored, 1 - data slice 3 is valid'}}},
'phy_rd_dqs_cfg0':{'OFFS':0x140,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY read DQS configuration register for data slice 0','FIELDS':{# 0x35
'reg_phy_rd_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 0'},
'reg_phy_rd_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 0'},
'reg_phy_rd_dqs_slave_ratio':{'r':(0,9),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 0'}}},# 0x35
'phy_rd_dqs_cfg1':{'OFFS':0x144,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY read DQS configuration register for data slice 1','FIELDS':{# 0x35
'reg_phy_rd_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 1'},
'reg_phy_rd_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 1'},
'reg_phy_rd_dqs_slave_ratio':{'r':(0,9),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 1'}}},# 0x35
'phy_rd_dqs_cfg2':{'OFFS':0x148,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY read DQS configuration register for data slice 2','FIELDS':{# 0x35
'reg_phy_rd_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 2'},
'reg_phy_rd_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 2'},
'reg_phy_rd_dqs_slave_ratio':{'r':(0,9),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 2'}}},# 0x35
'phy_rd_dqs_cfg3':{'OFFS':0x14C,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY read DQS configuration register for data slice 3','FIELDS':{# 0x35
'reg_phy_rd_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_rd_dqs_slave_force is 1, use this tap/delay value for read DQS slave DLL, data slice 3'},
'reg_phy_rd_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL, 1 - use provided in reg_phy_rd_dqs_slave_delay, data slice 3'},
'reg_phy_rd_dqs_slave_ratio':{'r':(0,9),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for the read DQS slave DLL, data slice 3'}}},# 0x35
'phy_wr_dqs_cfg0':{'OFFS':0x154,'DFLT':0x00000000,'RW':'RW','COMMENTS':'PHY write DQS configuration register for data slice 0','FIELDS':{# 0x0
'reg_phy_wr_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0'},
'reg_phy_wr_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0'},
'reg_phy_wr_dqs_slave_ratio':{'r':(0,9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio'}}},
'phy_wr_dqs_cfg1':{'OFFS':0x158,'DFLT':0x00000000,'RW':'RW','COMMENTS':'PHY write DQS configuration register for data slice 1','FIELDS':{# 0x0
'reg_phy_wr_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 1'},
'reg_phy_wr_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1'},
'reg_phy_wr_dqs_slave_ratio':{'r':(0,9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 1. Program manual training ratio'}}},
'phy_wr_dqs_cfg2':{'OFFS':0x15C,'DFLT':0x00000000,'RW':'RW','COMMENTS':'PHY write DQS configuration register for data slice 2','FIELDS':{# 0x0
'reg_phy_wr_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 2'},
'reg_phy_wr_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2'},
'reg_phy_wr_dqs_slave_ratio':{'r':(0,9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 2. Program manual training ratio'}}},
'phy_wr_dqs_cfg3':{'OFFS':0x160,'DFLT':0x00000000,'RW':'RW','COMMENTS':'PHY write DQS configuration register for data slice 3','FIELDS':{# 0x0
'reg_phy_wr_dqs_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 3'},
'reg_phy_wr_dqs_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3'},
'reg_phy_wr_dqs_slave_ratio':{'r':(0,9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 3. Program manual training ratio'}}},
'phy_we_cfg0':{'OFFS':0x168,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY FIFO write enable configuration register for data slice 0','FIELDS':{# 0x35
'reg_phy_fifo_we_in_delay':{'r':(12,20),'d':0,'c':'If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_0 slave DLL, data slice 0'},
'reg_phy_fifo_we_in_force':{'r':(11,11),'d':0,'c':'0 - use reg_phy_fifo_we_slave_ratio for fifo_we_0 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 0'},
'reg_phy_fifo_we_slave_ratio':{'r':(0,10),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 0. Program manual training ratio'}}},# 0x35
'phy_we_cfg1':{'OFFS':0x16C,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY FIFO write enable configuration register for data slice 1','FIELDS':{# 0x35
'reg_phy_fifo_we_in_delay':{'r':(12,20),'d':0,'c':'If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_1 slave DLL, data slice 1'},
'reg_phy_fifo_we_in_force':{'r':(11,11),'d':0,'c':'0 - use reg_phy_fifo_we_slave_ratio for fifo_we_1 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 1'},
'reg_phy_fifo_we_slave_ratio':{'r':(0,10),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 1. Program manual training ratio'}}},# 0x35
'phy_we_cfg2':{'OFFS':0x170,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY FIFO write enable configuration register for data slice 2','FIELDS':{# 0x35
'reg_phy_fifo_we_in_delay':{'r':(12,20),'d':0,'c':'If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_2 slave DLL, data slice 2'},
'reg_phy_fifo_we_in_force':{'r':(11,11),'d':0,'c':'0 - use reg_phy_fifo_we_slave_ratio for fifo_we_2 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 2'},
'reg_phy_fifo_we_slave_ratio':{'r':(0,10),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 2. Program manual training ratio'}}},# 0x35
'phy_we_cfg3':{'OFFS':0x174,'DFLT':0x00000040,'RW':'RW','COMMENTS':'PHY FIFO write enable configuration register for data slice 3','FIELDS':{# 0x35
'reg_phy_fifo_we_in_delay':{'r':(12,20),'d':0,'c':'If reg_phy_fifo_we_in_force is 1, use this tap/delay value for fifo_we_3 slave DLL, data slice 3'},
'reg_phy_fifo_we_in_force':{'r':(11,11),'d':0,'c':'0 - use reg_phy_fifo_we_slave_ratio for fifo_we_3 slave DLL, 1 - use provided in reg_phy_fifo_we_in_delay, data slice 3'},
'reg_phy_fifo_we_slave_ratio':{'r':(0,10),'d':0x40,'c':'Fraction of the clock cycle (256 = full period) for fifo_we_0 slave DLL, data slice 3. Program manual training ratio'}}},
'wr_data_slv0':{'OFFS':0x17C,'DFLT':0x00000080,'RW':'RW','COMMENTS':'PHY write data slave ratio configuration register for data slice 0','FIELDS':{# 0x40
'reg_phy_wr_data_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 0'},
'reg_phy_wr_data_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0'},
'reg_phy_wr_data_slave_ratio':{'r':(0,9),'d':0x80,'c':'Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 0. Program manual training ratio'}}},# 0x40
'wr_data_slv1':{'OFFS':0x180,'DFLT':0x00000080,'RW':'RW','COMMENTS':'PHY write data slave ratio configuration register for data slice 1','FIELDS':{# 0x40
'reg_phy_wr_data_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 1'},
'reg_phy_wr_data_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 1'},
'reg_phy_wr_data_slave_ratio':{'r':(0,9),'d':0x80,'c':'Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 1. Program manual training ratio'}}},# 0x40
'wr_data_slv2':{'OFFS':0x184,'DFLT':0x00000080,'RW':'RW','COMMENTS':'PHY write data slave ratio configuration register for data slice 2','FIELDS':{# 0x40
'reg_phy_wr_data_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 2'},
'reg_phy_wr_data_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 2'},
'reg_phy_wr_data_slave_ratio':{'r':(0,9),'d':0x80,'c':'Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 2. Program manual training ratio'}}},# 0x40
'wr_data_slv3':{'OFFS':0x188,'DFLT':0x00000080,'RW':'RW','COMMENTS':'PHY write data slave ratio configuration register for data slice 3','FIELDS':{# 0x40
'reg_phy_wr_data_slave_delay':{'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write data slave DLL, data slice 3'},
'reg_phy_wr_data_slave_force':{'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write data slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 3'},
'reg_phy_wr_data_slave_ratio':{'r':(0,9),'d':0x80,'c':'Fraction of the clock cycle (256 = full period) for the write data slave DLL, data slice 3. Program manual training ratio'}}},# 0x40
...
...
@@ -472,7 +472,7 @@ DDRC_DEFS={ #not all fields are defined currently
'reg_65':{'OFFS':0x194,'DFLT':0x00000000,'RW':'RW','COMMENTS':'Training control 3','FIELDS':{# 0x3c82
'reg_phy_ctrl_slave_delay':{'r':(18,19),'d':0,'c':'when reg_phy_rd_dqs_slave_force==1 this value (combined with bits 21:27 of reg_64) set address/command slave DLL'},
'reg_phy_dis_calib_rst':{'r':(17,17),'d':0,'c':'disable dll_claib from resetting Read Capture FIFO'},
'reg_phy_dis_calib_rst':{'r':(17,17),'d':0,'c':'disable dll_calib from resetting Read Capture FIFO'},
'reg_phy_use_rd_data_eye_level':{'r':(16,16),'d':0,'c':'Read Data Eye training control - 0 use fixed register data, 1 use data eye leveling data'},
'reg_phy_use_rd_dqs_gate_level':{'r':(15,15),'d':0,'c':'Read DQS Gate training control: 0 - used fixed data, 1 - use calculated data'},
'reg_phy_use_wr_level':{'r':(14,14),'d':0,'c':'Write leveling control: 0 - used programmed register data, 1 - use calculated data'},
...
...
@@ -592,28 +592,28 @@ DDRC_DEFS={ #not all fields are defined currently
# 'reg_ddrc_dis_collision_page_opt': {'r':(10,10),'d':0,'c':'Disable autoprecharge for collisions (write+write or read+write to the same address) when reg_ddrc_dis_wc==1'},
# 'reg_phy_wr_dqs_slave_delay': {'r':(11,19),'d':0,'c':'If reg_phy_wr_dqs_slave_force is 1, use this tap/delay value for write DQS slave DLL, data slice 0'},
# 'reg_phy_wr_dqs_slave_force': {'r':(10,10),'d':0,'c':'0 - use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL, 1 - use provided in reg_phy_wr_dqs_slave_delay, data slice 0'},
# 'reg_phy_wr_dqs_slave_ratio': {'r':( 0, 9),'d':0,'c':'Fraction of the clock cycle (256 = full period) for the write DQS slave DLL, data slice 0. Program manual training ratio'}}},
