1. ZC706 support 2. single script for multiple targets

README.md

@@ -65,6 +65,11 @@ the DRAM, not in the OCM. U-boot relocation functionality nicely skips actual re
 the source and destination addresses are the same) and the data memory is initialized when 192K
 OCM limit is not in effect anymore. 
 
+## SUPPORTED BOARDS
+
+* **Avnet MicroZed**
+* **Xilinx ZC706**
+* **Elphel 10393**
 
 ## INSTALLATION (see below for testing without U-boot installation)
 
@@ -118,6 +123,7 @@ New files include:
    suspect a hardware problem.
 3. Bitstream loading is not tested, current code does not enable level shifters - it may be
    more appropriate to do just before loading of the bitstream.
+4. Write level training for DDR memory doesn't work in MicroZed and ZC706
 
 ## Trademark notices
 

ezynq_uboot.py

@@ -90,6 +90,8 @@ UBOOT_CFG_DEFS=[
                 'DESCRIPTION':'LED ON/OFF before leaving lowlevel_init()'},              
     {'NAME':'LAST_PRINT_DEBUG',   'CONF_NAME':'CONFIG_EZYNQ_LAST_PRINT_DEBUG','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
                 'DESCRIPTION':'Output to UART before exiting arch_cpu_init()'},
+    {'NAME':'OCM_DDR_CHECKSUMS',   'CONF_NAME':'CONFIG_EZYNQ_OCM_DDR_CHECKSUMS','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
+                'DESCRIPTION':'Print OCM & DDR checksums'},
 ]
 # 
 # CONFIG_EZYNQ_BOOT_DEBUG = y # configure UARTx and send register dumps there
@@ -654,6 +656,31 @@ int arch_cpu_init(void)
             self.cfile+='\tuart_dump_regs(0x%08x,0x%08x, 16);\n'%(self.features.get_par_value_or_default('DUMP_DDR_LOW'),self.features.get_par_value_or_default('DUMP_DDR_HIGH'))
             self.cfile+='\tuart_puts("\\r\\n");\n'
             
+        if self.features.get_par_value_or_none('OCM_DDR_CHECKSUMS'):
+            self.cfile+='''/*Calculating the sums*/
+\tint i = 0;            
+\tint n = 3;            
+\tint sum;
+\tuart_puts("Memories data checksums:\\r\\n");
+\tfor(i=0;i<n;i++){
+\t\tuart_puts("Read ");
+\t\tuart_put_hex(i+1);
+\t\tuart_puts(": ");
+\t\ts = (int *) 0;
+\t\tsum=0;
+\t\twhile (s< ((int *)0x30000)) sum+=*s++;
+\t\tuart_puts("OCM= 0x");
+\t\tuart_put_hex(sum);
+\t\td = (int *) 0x4000000;
+\t\tsum=0;
+\t\twhile (d< ((int *)0x4030000)) sum+=*d++;
+\t\tuart_puts("  DDR= 0x");
+\t\tuart_put_hex(sum);
+\t\tuart_puts("\\r\\n");
+\t}
+\tuart_puts("\\r\\n");
+'''
+
 #         if 'uart_xmit' in self.sections:
 #             self.cfile+='\tuart_wait_tx_fifo_empty();\n'
         
@@ -664,12 +691,14 @@ int arch_cpu_init(void)
  */
 \tasm("add pc, pc, #0x4000000\\n\\t"
 "mov r0,r0\\n\\t"
+"mov r0,r0\\n\\t"
 "mov r0,r0" );
 '''
 # seems some delay is needed before remapping DDR memory
 #        self.cfile+='\tddrc_wait_queue_empty(); /* seems some delay is needed here before remapping DDR memory */\n'            
         self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )
 #        self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )
+            
         self.cfile+='\twritel(0, &scu_base->filter_start); /* Remap DDR to zero, FILTERSTART */\n'
         self.cfile+='''/* Device config APB, unlock the PCAP */
 \twritel(0x757BDF0D, &devcfg_base->unlock);

install_uboot.sh

@@ -108,4 +108,9 @@ fi
 echo "DONE. 
 FURTHER INSTRUCTIONS (TO GENERATE BOOT.BIN):
   cd u-boot-xlnx
-  ./makeuboot"
+  ./makeuboot <target> 
+
+SUPPORTED TARGETS:
+  ./makeuboot zynq_microzed_config
+  ./makeuboot zynq_zc706_config
+  ./makeuboot elphel393_config "

u-boot-tree/boards.cfg

@@ -322,6 +322,7 @@ zynq_afx_qspi                arm         armv7       zynq                xilinx
 zynq_afx_nand                arm         armv7       zynq                xilinx         zynq	zynq_afx:AFX_NAND
 zynq_microzed                arm         armv7       zynq                xilinx         zynq
 zynq_zc70x                   arm         armv7       zynq                xilinx         zynq
+zynq_zc706                   arm         armv7       zynq                xilinx         zynq
 zynq_zed                     arm         armv7       zynq                xilinx         zynq
 zynq_cse_qspi	     	     arm         armv7       zynq                xilinx         zynq	zynq_cse:CSE_QSPI
 zynq_cse_nand	     	     arm         armv7       zynq                xilinx         zynq	zynq_cse:CSE_NAND

u-boot-tree/include/configs/ezynq/ezynq393.h

@@ -44,6 +44,8 @@
 
 #define CONFIG_EZYNQ_DUMP_DDR_LOW  0x4000000  /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
 #define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff  /* DDR dump end   (deafault 0x40002ff) */
+
+#define CONFIG_EZYNQ_OCM_DDR_CHECKSUMS   Y
 #endif
 /* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
    If defined, each can be 0,1, ON or OFF */

u-boot-tree/include/configs/ezynq/ezynq_MT41J256M8HX15E.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Micron MT41J256M8HX15E DDR3 memory
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_EZYNQ_MT41J256M8HX15E_H
+#define __CONFIG_EZYNQ_MT41J256M8HX15E_H
+
+#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41J256M8HX15E /* Memory part number  (currently not used - derive some parameters later) */
+/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
+#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
+
+#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */
+#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */
+#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */
+#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       8  /* Memory chip bus width (not yet used) */
+#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.125 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
+#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RP             13.125 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
+#define CONFIG_EZYNQ_DDR_DS_T_RC             49.5/* Activate to Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        36.0 /* Minimal Row Active time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_FAW            30.0 /* Minimal running window for 4 page activates (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
+#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
+#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
+#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
+#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
+#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
+#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */
+#define CONFIG_EZYNQ_DDR_DS_T_WLMRD          40.0 /* Write leveling : time to the first DQS rising edge (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKE             7.5 /* CKE min pulse width (ns). 5.625  */
+#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
+#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
+#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
+
+
+#endif /* __CONFIG_EZYNQ_MT41J256M8HX15E_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z045_2FFG900C.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Xilinx XC7Z045_2FFG900C SoC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_XC7Z045_2FFG900C_H
+#define __CONFIG_XC7Z045_2FFG900C_H
+
+/* datasheet data for specific speed grades */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
+
+/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0
+#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504
+#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495
+#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520
+#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835
+#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465
+#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480
+#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550
+#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0
+/* Sorry for propOgation - this is how it is called in the tools */
+#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
+
+
+#endif /* __CONFIG_XC7Z045_2FFG900C */

u-boot-tree/include/configs/ezynq/zed_ezynq.h

@@ -38,14 +38,16 @@
 #define CONFIG_EZYNQ_DUMP_DDRC_LATE      N  /* Dump DDRC registers after DDR memory is initialized (depends on CONFIG_EZYNQ_BOOT_DEBUG) */
 #define CONFIG_EZYNQ_DUMP_TRAINING_EARLY N /* Training results registers before DDRC initialization */
 #define CONFIG_EZYNQ_DUMP_TRAINING_LATE  Y /* Training results registers after DDRC initialization */
-#define CONFIG_EZYNQ_DUMP_OCM            y /* Dump (some of) OCM data */
-#define CONFIG_EZYNQ_DUMP_DDR            y  /* Dump (some of) DDR data */
+#define CONFIG_EZYNQ_DUMP_OCM            Y /* Dump (some of) OCM data */
+#define CONFIG_EZYNQ_DUMP_DDR            Y  /* Dump (some of) DDR data */
 #if 1
 #define CONFIG_EZYNQ_DUMP_OCM_LOW        0x0   /* OCM dump start (deafault 0)     */
 #define CONFIG_EZYNQ_DUMP_OCM_HIGH     0x2ff   /* OCM dump end   (deafault 0x2ff, full - 0x2ffff) */
 
 #define CONFIG_EZYNQ_DUMP_DDR_LOW  0x4000000  /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
 #define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff  /* DDR dump end   (deafault 0x40002ff) */
+
+#define CONFIG_EZYNQ_OCM_DDR_CHECKSUMS   Y
 #endif
 /* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
    If defined, each can be 0,1, ON or OFF */
@@ -96,9 +98,9 @@ Red LED - pullup, input - on,
 #define CONFIG_EZYNQ_DDR_ARB_PAGE_BANK      N        /*  Enable Arbiter prioritization based on page/bank match */
 #define CONFIG_EZYNQ_DDR_ECC                Disabled /*  Enable ECC for the DDR memory */
 #define CONFIG_EZYNQ_DDR_BUS_WIDTH          32       /*  SoC DDR bus width */
-#define CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL  n        /*  Automatically train write leveling during initialization */
-#define CONFIG_EZYNQ_DDR_TRAIN_READ_GATE    n        /*  Automatically train read gate timing during initialization */
-#define CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE     n        /*  Automatically train data eye during initialization */
+#define CONFIG_EZYNQ_DDR_TRAIN_WRITE_LEVEL  N        /*  [doesn't work yet] Automatically train write leveling during initialization */
+#define CONFIG_EZYNQ_DDR_TRAIN_READ_GATE    N        /*  Automatically train read gate timing during initialization */
+#define CONFIG_EZYNQ_DDR_TRAIN_DATA_EYE     N        /*  Automatically train data eye during initialization */
 #define CONFIG_EZYNQ_DDR_CLOCK_STOP_EN      0        /*  Enable clock stop */
 #define CONFIG_EZYNQ_DDR_USE_INTERNAL_VREF  0        /*  Use internal Vref */
 

u-boot-tree/include/configs/zynq_zc706.h

+/*
+ * (C) Copyright 2012 Xilinx
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq_common.h for Zynq common configs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC706_H
+#define __CONFIG_ZYNQ_ZC706_H
+
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+
+#undef CONFIG_SYS_TEXT_BASE
+#include <configs/zynq_common.h>
+#include <configs/ezynq/ezynq_MT41J256M8HX15E.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
+#include <configs/ezynq/ezynq_XC7Z045_2FFG900C.h>
+#include <configs/ezynq/zc706_ezynq.h>
+
+#define CONFIG_CMD_MEMTEST
+//#undef CONFIG_EZYNQ_BOOT_DEBUG 
+#undef CONFIG_EZYNQ_LED_DEBUG
+
+/* twice slower */
+#undef CONFIG_ZYNQ_SERIAL_CLOCK0
+/*#define CONFIG_ZYNQ_SERIAL_CLOCK0	25000000*/
+#define CONFIG_ZYNQ_SERIAL_CLOCK0	1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
+#undef CONFIG_ZYNQ_SERIAL_CLOCK1
+/*#define CONFIG_ZYNQ_SERIAL_CLOCK1	25000000*/
+#define CONFIG_ZYNQ_SERIAL_CLOCK1	1000000 * (CONFIG_EZYNQ_CLK_UART_MHZ)
+
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_SYS_PROMPT
+#undef CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOOTDELAY	-1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_PROMPT		"ezynq> "
+
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* Physical start address of SDRAM. _Must_ be 0 here. */
+#define CONFIG_ENV_SIZE		        1400
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#if 0
+  #define CONFIG_SYS_TEXT_BASE		0x04000000 /*with 0x04000000 - does not get to the low_Level_init? */
+#else
+  //#define CONFIG_SYS_TEXT_BASE		0x00000000 //0x04000000 with 0x04000000 - does not get to the low_Level_init?
+#endif
+/*
+#define CONFIG_EZYNQ_SKIP_DDR
+*/
+#define CONFIG_EZYNQ_SKIP_CLK
+
+//undefs
+
+/* undefs */
+/*#undef CONFIG_FS_FAT */
+/* #undef CONFIG_SUPPORT_VFAT */
+/* #undef CONFIG_CMD_FAT */
+/* http://lists.denx.de/pipermail/u-boot/2003-October/002631.html */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+/* CONFIG_FS_FAT=y */
+
+/* disable PL*/
+#undef CONFIG_FPGA
+#undef CONFIG_FPGA_XILINX
+#undef CONFIG_FPGA_ZYNQPL
+#undef CONFIG_CMD_FPGA
+
+#undef CONFIG_CMD_EXT2
+
+#undef CONFIG_CMD_CACHE
+
+// #undef DEBUG
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_SYS_LONGHELP
+
+/* redefine env settings*/
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0a:35:00:01:22\0"	\
+	"kernel_image=uImage\0"	\
+	"ramdisk_image=uramdisk.image.gz\0"	\
+ 	"devicetree_image=devicetree.dtb\0"	\
+	"bitstream_image=system.bit.bin\0"	\
+	"loadbit_addr=0x100000\0"	\
+	"kernel_size=0x500000\0"	\
+	"devicetree_size=0x20000\0"	\
+	"ramdisk_size=0x5E0000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"sdboot=echo Copying Linux from SD to RAM... && " \
+		"mmcinfo && " \
+		"fatload mmc 0 0x3000000 ${kernel_image} && " \
+		"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
+		"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
+		"nand read 0x3000000 0x100000 ${kernel_size} && " \
+		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0"
+/*  */
+
+#endif /* __CONFIG_ZYNQ_ZC706_H */

u-boot-tree/makeuboot

 #!/bin/bash
+
+if [ ! $1 ]; then
+  echo "  Usage:  
+      ./makeuboot <target> 
+  Supported targets:
+      ./makeuboot zynq_microzed_config
+      ./makeuboot zynq_zc706_config
+      ./makeuboot elphel393_config
+  "
+  exit -1
+fi
+
 . ./initenv
 make clean
-make zynq_microzed_config
+make $1
 make include/autoconf.mk
 echo "Running ezynqcfg.py for the first time - u-boot.bin length is not known yet, generating arch/arm/cpu/armv7/zynq/ezynq.c"
 ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/ezynq.c

u-boot-tree/makeuboot393

-#!/bin/bash
-. ./initenv
-make clean
-make elphel393_config
-make include/autoconf.mk
-echo "Running ezynqcfg.py for the first time - u-boot.bin length is not known yet, generating arch/arm/cpu/armv7/zynq/ezynq.c"
-ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/ezynq.c
-
-make
-
-echo "Running ezynqcfg.py for the second time - u-boot.bin length is known and will be used in the RBL header"
-echo "Other files are already created, repeating it here just to remind their paths"
-ezynq/ezynqcfg.py -c include/autoconf.mk -o boot_head.bin --uboot u-boot.bin --html u-boot.html --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/ezynq.c
-cat boot_head.bin u-boot.bin > boot.bin