1. ZC706 support 2. single script for multiple targets (3aa24fcd) · Commits · Elphel / ezynq

README.md

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -65,6 +65,11 @@ the DRAM, not in the OCM. U-boot relocation functionality nicely skips actual re
	the source and destination addresses are the same) and the data memory is initialized when 192K		the source and destination addresses are the same) and the data memory is initialized when 192K
	OCM limit is not in effect anymore.		OCM limit is not in effect anymore.

			## SUPPORTED BOARDS

			* Avnet MicroZed
			* Xilinx ZC706
			* Elphel 10393

	## INSTALLATION (see below for testing without U-boot installation)		## INSTALLATION (see below for testing without U-boot installation)

	@@ -118,6 +123,7 @@ New files include:
	suspect a hardware problem.		suspect a hardware problem.
	3. Bitstream loading is not tested, current code does not enable level shifters - it may be		3. Bitstream loading is not tested, current code does not enable level shifters - it may be
	more appropriate to do just before loading of the bitstream.		more appropriate to do just before loading of the bitstream.
			4. Write level training for DDR memory doesn't work in MicroZed and ZC706

	## Trademark notices		## Trademark notices

ezynq_uboot.py

+30 −1

Original line number	Original line	Diff line number	Diff line
	@@ -90,6 +90,8 @@ UBOOT_CFG_DEFS=[
	'DESCRIPTION':'LED ON/OFF before leaving lowlevel_init()'},		'DESCRIPTION':'LED ON/OFF before leaving lowlevel_init()'},
	{'NAME':'LAST_PRINT_DEBUG', 'CONF_NAME':'CONFIG_EZYNQ_LAST_PRINT_DEBUG','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,		{'NAME':'LAST_PRINT_DEBUG', 'CONF_NAME':'CONFIG_EZYNQ_LAST_PRINT_DEBUG','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
	'DESCRIPTION':'Output to UART before exiting arch_cpu_init()'},		'DESCRIPTION':'Output to UART before exiting arch_cpu_init()'},
			{'NAME':'OCM_DDR_CHECKSUMS', 'CONF_NAME':'CONFIG_EZYNQ_OCM_DDR_CHECKSUMS','TYPE':'B','MANDATORY':False,'DERIVED':False,'DEFAULT':None,
			'DESCRIPTION':'Print OCM & DDR checksums'},
	]		]
	#		#
	# CONFIG_EZYNQ_BOOT_DEBUG = y # configure UARTx and send register dumps there		# CONFIG_EZYNQ_BOOT_DEBUG = y # configure UARTx and send register dumps there
	@@ -654,6 +656,31 @@ int arch_cpu_init(void)
	self.cfile+='\tuart_dump_regs(0x%08x,0x%08x, 16);\n'%(self.features.get_par_value_or_default('DUMP_DDR_LOW'),self.features.get_par_value_or_default('DUMP_DDR_HIGH'))		self.cfile+='\tuart_dump_regs(0x%08x,0x%08x, 16);\n'%(self.features.get_par_value_or_default('DUMP_DDR_LOW'),self.features.get_par_value_or_default('DUMP_DDR_HIGH'))
	self.cfile+='\tuart_puts("\\r\\n");\n'		self.cfile+='\tuart_puts("\\r\\n");\n'

			if self.features.get_par_value_or_none('OCM_DDR_CHECKSUMS'):
			self.cfile+='''/Calculating the sums/
			\tint i = 0;
			\tint n = 3;
			\tint sum;
			\tuart_puts("Memories data checksums:\\r\\n");
			\tfor(i=0;i<n;i++){
			\t\tuart_puts("Read ");
			\t\tuart_put_hex(i+1);
			\t\tuart_puts(": ");
			\t\ts = (int *) 0;
			\t\tsum=0;
			\t\twhile (s< ((int )0x30000)) sum+=s++;
			\t\tuart_puts("OCM= 0x");
			\t\tuart_put_hex(sum);
			\t\td = (int *) 0x4000000;
			\t\tsum=0;
			\t\twhile (d< ((int )0x4030000)) sum+=d++;
			\t\tuart_puts(" DDR= 0x");
			\t\tuart_put_hex(sum);
			\t\tuart_puts("\\r\\n");
			\t}
			\tuart_puts("\\r\\n");
			'''

	# if 'uart_xmit' in self.sections:		# if 'uart_xmit' in self.sections:
	# self.cfile+='\tuart_wait_tx_fifo_empty();\n'		# self.cfile+='\tuart_wait_tx_fifo_empty();\n'

	@@ -664,12 +691,14 @@ int arch_cpu_init(void)
	*/		*/
	\tasm("add pc, pc, #0x4000000\\n\\t"		\tasm("add pc, pc, #0x4000000\\n\\t"
	"mov r0,r0\\n\\t"		"mov r0,r0\\n\\t"
			"mov r0,r0\\n\\t"
	"mov r0,r0" );		"mov r0,r0" );
	'''		'''
	# seems some delay is needed before remapping DDR memory		# seems some delay is needed before remapping DDR memory
	# self.cfile+='\tddrc_wait_queue_empty(); /* seems some delay is needed here before remapping DDR memory */\n'		# self.cfile+='\tddrc_wait_queue_empty(); /* seems some delay is needed here before remapping DDR memory */\n'
	self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )		self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )
	# self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )		# self._cp_led('LED_CHECKPOINT_9') # After relocation to DDR (to 0x4000000+ )

	self.cfile+='\twritel(0, &scu_base->filter_start); /* Remap DDR to zero, FILTERSTART */\n'		self.cfile+='\twritel(0, &scu_base->filter_start); /* Remap DDR to zero, FILTERSTART */\n'
	self.cfile+='''/* Device config APB, unlock the PCAP */		self.cfile+='''/* Device config APB, unlock the PCAP */
	\twritel(0x757BDF0D, &devcfg_base->unlock);		\twritel(0x757BDF0D, &devcfg_base->unlock);

install_uboot.sh

+6 −1

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	@@ -108,4 +108,9 @@ fi
	echo "DONE.		echo "DONE.
	FURTHER INSTRUCTIONS (TO GENERATE BOOT.BIN):		FURTHER INSTRUCTIONS (TO GENERATE BOOT.BIN):
	cd u-boot-xlnx		cd u-boot-xlnx
	./makeuboot"		./makeuboot <target>

			SUPPORTED TARGETS:
			./makeuboot zynq_microzed_config
			./makeuboot zynq_zc706_config
			./makeuboot elphel393_config "

u-boot-tree/boards.cfg

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -322,6 +322,7 @@ zynq_afx_qspi arm armv7 zynq xilinx
	zynq_afx_nand arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND		zynq_afx_nand arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND
	zynq_microzed arm armv7 zynq xilinx zynq		zynq_microzed arm armv7 zynq xilinx zynq
	zynq_zc70x arm armv7 zynq xilinx zynq		zynq_zc70x arm armv7 zynq xilinx zynq
			zynq_zc706 arm armv7 zynq xilinx zynq
	zynq_zed arm armv7 zynq xilinx zynq		zynq_zed arm armv7 zynq xilinx zynq
	zynq_cse_qspi arm armv7 zynq xilinx zynq zynq_cse:CSE_QSPI		zynq_cse_qspi arm armv7 zynq xilinx zynq zynq_cse:CSE_QSPI
	zynq_cse_nand arm armv7 zynq xilinx zynq zynq_cse:CSE_NAND		zynq_cse_nand arm armv7 zynq xilinx zynq zynq_cse:CSE_NAND

u-boot-tree/include/configs/ezynq/ezynq393.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -44,6 +44,8 @@

	#define CONFIG_EZYNQ_DUMP_DDR_LOW 0x4000000 /* DDR dump start (deafault 0x4000000, start of the OCM copy) */		#define CONFIG_EZYNQ_DUMP_DDR_LOW 0x4000000 /* DDR dump start (deafault 0x4000000, start of the OCM copy) */
	#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff /* DDR dump end (deafault 0x40002ff) */		#define CONFIG_EZYNQ_DUMP_DDR_HIGH 0x40002ff /* DDR dump end (deafault 0x40002ff) */

			#define CONFIG_EZYNQ_OCM_DDR_CHECKSUMS Y
	#endif		#endif
	/* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set		/* Turning LED on/off at different stages of the boot process. Requires CONFIG_EZYNQ_LED_DEBUG and CONFIG_EZYNQ_BOOT_DEBUG to be set
	If defined, each can be 0,1, ON or OFF */		If defined, each can be 0,1, ON or OFF */