some cleanup

ezynq_uboot.py

@@ -691,7 +691,13 @@ int arch_cpu_init(void)
 \twhile (d < ((int *) 0x30000)) *d++=*s++;
 
 \tddrc_wait_queue_empty(); /* Wait no commands are pending in DDRC queue */   
-
+/*
+ * Below is a hack - copying the same data to low SDRAM again - probably just a delay.
+ * Waiting for ddrc_wait_queue_empty() alone is not sufficient - some of the
+ * generated images work always, some - half times, some - never, dependent on 
+ * seemingly unrelated changes. With this extra delay all seems fine.
+ * Better understanding of the original problem and a fix is needed.
+ */
 \ts= (int *) 0x4000000;
 \td= (int *) 0;
 \twhile (d < ((int *) 0x30000)) *d++=*s++;

u-boot-tree/include/configs/ezynq/ezynq393.h

@@ -69,8 +69,7 @@
 #define CONFIG_EZYNQ_NAND__SLOW
 
 #define CONFIG_EZYNQ_MIO_ETH_0__SLOW
-/* TODO: enable MDIO */
-/*#define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW  */
+#define CONFIG_EZYNQ_MIO_ETH_MDIO__SLOW
 
 #define CONFIG_EZYNQ_MIO_USB_0__SLOW
 #define CONFIG_EZYNQ_MIO_USB_0__PULLUP
@@ -219,7 +218,7 @@ output (or undefined) -   off
 //  #define CONFIG_EZYNQ_MIO_INOUT_53      OUT     /* Make output, do not set data. Will be set after debug will be over */
 
 
-  #define CONFIG_EZYNQ_MIO_GPIO_OUT_53     0     /* Set selected GPIO output to 0/1 */
+/*  #define CONFIG_EZYNQ_MIO_GPIO_OUT_53     0 */    /* Set selected GPIO output to 0/1 */
   #undef  CONFIG_EZYNQ_DDR_DS_CKE
   #define CONFIG_EZYNQ_DDR_DS_CKE               4   /* CKE min pulse width (in tCK) */
 
@@ -228,7 +227,7 @@ output (or undefined) -   off
 
 
 
-  #define CONFIG_EZYNQ_LED_DEBUG          53     /* toggle LED during boot - temporary, normal use - MDIO_D */
+/*  #define CONFIG_EZYNQ_LED_DEBUG          53 */    /* toggle LED during boot - temporary, normal use - MDIO_D */
   #define CONFIG_EZYNQ_UART_DEBUG_USE_LED    N    /* turn on/off LED while waiting for transmit FIFO not full */
 
   #define CONFIG_EZYNQ_SILICON               3 /* 3 */        /* Silicon revision */