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ezynq
Commit 1cf29106 authored by Andrey Filippov's avatar Andrey Filippov
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added second pass to specify correct u-boot.bin image length for the RBL header

parent 0fcfd161
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Showing with 77 additions and 69 deletions
ezynq_clk.py
View file @ 1cf29106
...@@ -376,6 +376,8 @@ class EzynqClk: ...@@ -376,6 +376,8 @@ class EzynqClk:
return set([pll for pll in self.pll_fdivs]) return set([pll for pll in self.pll_fdivs])
def html_list_clocks(self,html_file): def html_list_clocks(self,html_file):
if not html_file:
return
def list_with_children(name): def list_with_children(name):
result = [name] result = [name]
for kid_name in self.iface_divs: for kid_name in self.iface_divs:
......
ezynq_ddrc_defs.py
View file @ 1cf29106
...@@ -47,15 +47,15 @@ DDRC_DEFS={ #not all fields are defined currently ...@@ -47,15 +47,15 @@ DDRC_DEFS={ #not all fields are defined currently
'hpr_reg': {'OFFS': 0x008,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x3c0780f 'hpr_reg': {'OFFS': 0x008,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x3c0780f
'reg_ddrc_hpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'HPR queue transactions to be served after going critical'}, 'reg_ddrc_hpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'HPR queue transactions to be served after going critical'},
'reg_ddrc_hpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks HPR may be starved before going critical'}, 'reg_ddrc_hpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks HPR may be starved before going critical'},
'reg_ddrc_hpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number off 32x clocks HPR queue is guaranteed to be non-critical'}}}, 'reg_ddrc_hpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number of 32x clocks HPR queue is guaranteed to be non-critical'}}},
'lpr_reg': {'OFFS': 0x00C,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x2001001 'lpr_reg': {'OFFS': 0x00C,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x2001001
'reg_ddrc_lpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'LPR queue transactions to be served after going critical'}, # 0x8 'reg_ddrc_lpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'LPR queue transactions to be served after going critical'}, # 0x8
'reg_ddrc_lpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks LPR may be starved before going critical'}, # 0x2 'reg_ddrc_lpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks LPR may be starved before going critical'}, # 0x2
'reg_ddrc_lpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number off 32x clocks LPR queue is guaranteed to be non-critical'}}}, #0x1 'reg_ddrc_lpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number of 32x clocks LPR queue is guaranteed to be non-critical'}}}, #0x1
'wr_reg': {'OFFS': 0x010,'DFLT':0x0007F80F,'RW':'RW','FIELDS':{ #0x14001 'wr_reg': {'OFFS': 0x010,'DFLT':0x0007F80F,'RW':'RW','FIELDS':{ #0x14001
'reg_ddrc_w_max_starve_x32': {'r':(15,25),'d':0xF,'c':'Number of 32x clocks write queue may be starved before going critical'},#0 x2 # opposite sequence from HPR,LPR 'reg_ddrc_w_max_starve_x32': {'r':(15,25),'d':0xF,'c':'Number of 32x clocks write queue may be starved before going critical'},#0 x2 # opposite sequence from HPR,LPR
'reg_ddrc_w_xact_run_length': {'r':(11,14),'d':0xF,'c':'write queue transactions to be served after going critical'}, # 0x8 'reg_ddrc_w_xact_run_length': {'r':(11,14),'d':0xF,'c':'write queue transactions to be served after going critical'}, # 0x8
'reg_ddrc_w_min_non_critical_x32': {'r':( 0,10),'d':0xF,'c':'Number off 32x clocks write queue is guaranteed to be non-critical'}}}, # 0x2 'reg_ddrc_w_min_non_critical_x32': {'r':( 0,10),'d':0xF,'c':'Number of 32x clocks write queue is guaranteed to be non-critical'}}}, # 0x2
'dram_param_reg0': {'OFFS': 0x014,'DFLT':0x00041016,'RW':'RW','FIELDS':{ # 0x4281a 'dram_param_reg0': {'OFFS': 0x014,'DFLT':0x00041016,'RW':'RW','FIELDS':{ # 0x4281a
'reg_ddrc_post_selfref_gap_x32': {'r':(14,20),'d':0x10,'c':'DRAM-related, minimal time after self refresh'}, #0x10 'reg_ddrc_post_selfref_gap_x32': {'r':(14,20),'d':0x10,'c':'DRAM-related, minimal time after self refresh'}, #0x10
'reg_ddrc_t_rfc_min': {'r':( 6,15),'d':0x40,'c':'Dynamic, tRFC'}, #0xa0 'reg_ddrc_t_rfc_min': {'r':( 6,15),'d':0x40,'c':'Dynamic, tRFC'}, #0xa0
......
ezynqcfg.py
View file @ 1cf29106
...@@ -40,6 +40,7 @@ parser.add_argument('--html', help='Generate HTML map of MIO, save to the specif ...@@ -40,6 +40,7 @@ parser.add_argument('--html', help='Generate HTML map of MIO, save to the specif
parser.add_argument('--html-mask', help='Bit mask of what data to include in the HTML MIO map') parser.add_argument('--html-mask', help='Bit mask of what data to include in the HTML MIO map')
#parser.add_argument('-i', '--include', help='Generate include file for u-boot') #parser.add_argument('-i', '--include', help='Generate include file for u-boot')
parser.add_argument('-l', '--lowlevel', help='path to the lowlevel.c file to be generated for u-boot') parser.add_argument('-l', '--lowlevel', help='path to the lowlevel.c file to be generated for u-boot')
parser.add_argument('-u', '--uboot', help='path to the u-boot.bin to get it\'s length (second pass, when u-boot.bin is already generated)')
args = parser.parse_args() args = parser.parse_args()
#print args #print args
...@@ -324,14 +325,12 @@ mio_regs.output_mio(html_file,MIO_HTML_MASK) ...@@ -324,14 +325,12 @@ mio_regs.output_mio(html_file,MIO_HTML_MASK)
# def process_mio(self,raw_configs,warn): # def process_mio(self,raw_configs,warn):
# def output_mio(self,f,MIO_HTML_MASK) # def output_mio(self,f,MIO_HTML_MASK)
# setregs_mio(self,current_reg_sets,force=True): # setregs_mio(self,current_reg_sets,force=True):
clk.html_list_clocks(html_file) clk.html_list_clocks(html_file)
#output_mio(registers,f,mio,MIO_HTML_MASK)
ddr.calculate_dependent_pars(ddr_mhz) ddr.calculate_dependent_pars(ddr_mhz)
ddr.pre_validate() # before applying default values (some timings should be undefined, not defaults) ddr.pre_validate() # before applying default values (some timings should be undefined, not defaults)
ddr.check_missing_features() #and apply default values ddr.check_missing_features() #and apply default values
ddr.html_list_features(html_file) #verify /fix values after defaults are applied ddr.html_list_features(html_file) #verify /fix values after defaults are applied
#clk.calculate_dependent_pars() #clk.calculate_dependent_pars()
...@@ -435,36 +434,32 @@ for index,segment in enumerate(segments): ...@@ -435,36 +434,32 @@ for index,segment in enumerate(segments):
segment_dict[segment['NAME']]=segment segment_dict[segment['NAME']]=segment
#for index,segment in enumerate(segments): #for index,segment in enumerate(segments):
# print index,':', segment # print index,':', segment
for segment in segments:
start=segment['FROM']
end=segment['TO']
show_bit_fields= (MIO_HTML_MASK & 0x100,MIO_HTML_MASK & 0x800)[segment['NAME']=='MIO']
show_comments= MIO_HTML_MASK & 0x200
filter_fields=not MIO_HTML_MASK & 0x400
all_used_fields= False
ezynq_registers.print_html_reg_header(html_file,
segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]),
show_bit_fields, show_comments, filter_fields)
# print segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]), start,end
ezynq_registers.print_html_registers(html_file,
reg_sets[:end],
start,
show_bit_fields,
show_comments,
filter_fields,
all_used_fields)
ezynq_registers.print_html_reg_footer(html_file)
if html_file: if html_file:
for segment in segments:
start=segment['FROM']
end=segment['TO']
show_bit_fields= (MIO_HTML_MASK & 0x100,MIO_HTML_MASK & 0x800)[segment['NAME']=='MIO']
show_comments= MIO_HTML_MASK & 0x200
filter_fields=not MIO_HTML_MASK & 0x400
all_used_fields= False
ezynq_registers.print_html_reg_header(html_file,
segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]),
show_bit_fields, show_comments, filter_fields)
# print segment['TITLE']+" (%s)"%(('U-BOOT','RBL')[segment['RBL']]), start,end
ezynq_registers.print_html_registers(html_file,
reg_sets[:end],
start,
show_bit_fields,
show_comments,
filter_fields,
all_used_fields)
ezynq_registers.print_html_reg_footer(html_file)
html_file.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>") html_file.write('<h4>Total number of registers set up in the RBL header is <b>'+str(num_rbl_regs)+"</b> of maximal 256</h4>")
if num_rbl_regs<len(reg_sets): if num_rbl_regs<len(reg_sets):
html_file.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b></h4>") html_file.write('<h4>Number of registers set up in u-boot is <b>'+str(len(reg_sets)-num_rbl_regs)+"</b></h4>")
#
if MIO_HTML:
html_file.close html_file.close
#if args.verbosity >= 1:
# print registers
image =[ 0 for k in range (0x8c0/4)] image =[ 0 for k in range (0x8c0/4)]
#image_generator (image, registers, user_def,start_offset,ocm_len,start_exec) #image_generator (image, registers, user_def,start_offset,ocm_len,start_exec)
...@@ -472,53 +467,61 @@ image =[ 0 for k in range (0x8c0/4)] ...@@ -472,53 +467,61 @@ image =[ 0 for k in range (0x8c0/4)]
#CONFIG_EZYNQ_BOOT_OCM_OFFSET= 0x8C0 # start of OCM data relative to the flash image start >=0x8C0, 63-bytes aligned #CONFIG_EZYNQ_BOOT_OCM_OFFSET= 0x8C0 # start of OCM data relative to the flash image start >=0x8C0, 63-bytes aligned
#CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0x30000 # number of bytes to load to the OCM memory, <= 0x30000 #CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0x30000 # number of bytes to load to the OCM memory, <= 0x30000
#CONFIG_EZYNQ_START_EXEC= 0x20 # number of bytes to load to the OCM memory, <= 0x30000 #CONFIG_EZYNQ_START_EXEC= 0x20 # number of bytes to load to the OCM memory, <= 0x30000
if (args.uboot):
try:
uboot_image_len=os.path.getsize(args.uboot)
print 'Using %s to get image length - it is %i (0x%x) bytes'%(os.path.abspath(args.uboot),uboot_image_len,uboot_image_len)
except:
print 'Specified u-boot.bin file: %s (%s) not found'%(args.uboot,os.path.abspath(args.uboot))
else:
uboot_image_len=int(raw_options['CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH'],0)
print 'No u-boot.bin path specified, using provided CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH as image size of %i (0x%x) bytes for the RBL header'%(uboot_image_len,uboot_image_len)
image_generator (image, image_generator (image,
reg_sets[:num_rbl_regs], # reg_sets[:num_rbl_regs], #
#registers, #registers,
raw_options, raw_options,
int(raw_options['CONFIG_EZYNQ_BOOT_USERDEF'],0), # user_def int(raw_options['CONFIG_EZYNQ_BOOT_USERDEF'],0), # user_def
int(raw_options['CONFIG_EZYNQ_BOOT_OCM_OFFSET'],0), # ocm_offset, int(raw_options['CONFIG_EZYNQ_BOOT_OCM_OFFSET'],0), # ocm_offset,
int(raw_options['CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH'],0), #ocm_len, uboot_image_len, #ocm_len,
int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec) int(raw_options['CONFIG_EZYNQ_START_EXEC'],0)) #start_exec)
if args.outfile: if args.outfile:
print 'Generating binary output ',os.path.abspath(args.outfile)
write_image(image,args.outfile) write_image(image,args.outfile)
if (args.lowlevel):
# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'MIO','TITLE':'MIO registers configuration'})
# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'DDR0','TITLE':'DDR registers configuration'})
# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'MIO','TITLE':'MIO registers configuration'}) # segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock registers configuration'})
# segments.append({'TO':len(reg_sets),'RBL':True,'NAME':'DDR0','TITLE':'DDR registers configuration'}) # segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'PLL','TITLE':'Registers to switch to PLL'})
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_INIT','TITLE':'Registers to initialize UART'})
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'CLK','TITLE':'Clock registers configuration'}) # segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DCI','TITLE':'DDR DCI Calibration'})
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'PLL','TITLE':'Registers to switch to PLL'}) # segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'})
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'UART_INIT','TITLE':'Registers to initialize UART'}) #CONFIG_EZYNQ_UART_DEBUG_USE_LED
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DCI','TITLE':'DDR DCI Calibration'}) if 'SLCR_LOCK_UNLOCK' in segment_dict:
# segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDR_START','TITLE':'DDR initialization start'}) u_boot.make_slcr_lock_unlock (reg_sets[segment_dict['SLCR_LOCK_UNLOCK']['FROM']:segment_dict['SLCR_LOCK_UNLOCK']['TO']])
#CONFIG_EZYNQ_UART_DEBUG_USE_LED if 'LED' in segment_dict:
if 'SLCR_LOCK_UNLOCK' in segment_dict: u_boot.make_led_on_off(reg_sets[segment_dict['LED']['FROM']:segment_dict['LED']['TO']])
u_boot.make_slcr_lock_unlock (reg_sets[segment_dict['SLCR_LOCK_UNLOCK']['FROM']:segment_dict['SLCR_LOCK_UNLOCK']['TO']])
if 'LED' in segment_dict:
u_boot.make_led_on_off(reg_sets[segment_dict['LED']['FROM']:segment_dict['LED']['TO']])
if 'CLK' in segment_dict:
u_boot.registers_setup (reg_sets[segment_dict['CLK']['FROM']:segment_dict['CLK']['TO']],clk,num_rbl_regs)
if 'PLL' in segment_dict:
u_boot.pll_setup (reg_sets[segment_dict['PLL']['FROM']:segment_dict['PLL']['TO']],clk)
if 'UART_INIT' in segment_dict:
u_boot.uart_init (reg_sets[segment_dict['UART_INIT']['FROM']:segment_dict['UART_INIT']['TO']])
if 'UART_XMIT' in segment_dict:
u_boot.uart_transmit (reg_sets[segment_dict['UART_XMIT']['FROM']:segment_dict['UART_XMIT']['TO']])
u_boot.make_ddrc_register_dump()
u_boot.make_slcr_register_dump()
#if not u_boot.features.get_par_value_or_none('BOOT_DEBUG') is None:
if 'DCI' in segment_dict:
u_boot.dci_calibration(reg_sets[segment_dict['DCI']['FROM']:segment_dict['DCI']['TO']])
if 'DDR_START' in segment_dict:
u_boot.ddr_start (reg_sets[segment_dict['DDR_START']['FROM']:segment_dict['DDR_START']['TO']])
if 'DDRC_STA' in segment_dict:
u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']])
#segments.append({'TO':len(reg_sets),'RBL':False,'NAME':'DDRC_STA','TITLE':'resgister to test DDRC comamnd queue status - listed out of sequence'}) if 'CLK' in segment_dict:
u_boot.registers_setup (reg_sets[segment_dict['CLK']['FROM']:segment_dict['CLK']['TO']],clk,num_rbl_regs)
if 'PLL' in segment_dict:
u_boot.pll_setup (reg_sets[segment_dict['PLL']['FROM']:segment_dict['PLL']['TO']],clk)
if 'UART_INIT' in segment_dict:
u_boot.uart_init (reg_sets[segment_dict['UART_INIT']['FROM']:segment_dict['UART_INIT']['TO']])
if 'UART_XMIT' in segment_dict:
u_boot.uart_transmit (reg_sets[segment_dict['UART_XMIT']['FROM']:segment_dict['UART_XMIT']['TO']])
u_boot.make_ddrc_register_dump()
u_boot.make_slcr_register_dump()
#if not u_boot.features.get_par_value_or_none('BOOT_DEBUG') is None:
if 'DCI' in segment_dict:
u_boot.dci_calibration(reg_sets[segment_dict['DCI']['FROM']:segment_dict['DCI']['TO']])
if 'DDR_START' in segment_dict:
u_boot.ddr_start (reg_sets[segment_dict['DDR_START']['FROM']:segment_dict['DDR_START']['TO']])
if 'DDRC_STA' in segment_dict:
u_boot.ddrc_wait_empty_queue(reg_sets[segment_dict['DDRC_STA']['FROM']:segment_dict['DDRC_STA']['TO']])
u_boot.make_lowlevel_init() u_boot.make_lowlevel_init()
u_boot.output_c_file(args.lowlevel) u_boot.output_c_file(args.lowlevel)
#print u_boot.get_c_file() #print u_boot.get_c_file()
test.mk
View file @ 1cf29106
...@@ -107,7 +107,7 @@ CONFIG_EZYNQ_MIO_UART_1=48 # 8+4*N ...@@ -107,7 +107,7 @@ CONFIG_EZYNQ_MIO_UART_1=48 # 8+4*N
#RBL header parameters #RBL header parameters
CONFIG_EZYNQ_BOOT_USERDEF= 0x1234567 # will be saved in the file header CONFIG_EZYNQ_BOOT_USERDEF= 0x1234567 # will be saved in the file header
CONFIG_EZYNQ_BOOT_OCM_OFFSET= 0x8C0 # start of OCM data relative to the flash image start >=0x8C0, 63-bytes aligned CONFIG_EZYNQ_BOOT_OCM_OFFSET= 0x8C0 # start of OCM data relative to the flash image start >=0x8C0, 63-bytes aligned
CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0#0x30000 # number of bytes to load to the OCM memory, <= 0x30000 CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0x30000 # number of bytes to load to the OCM memory, <= 0x30000
CONFIG_EZYNQ_START_EXEC= 0x00 # start of execution address CONFIG_EZYNQ_START_EXEC= 0x00 # start of execution address
......
u-boot-tree/makeuboot
View file @ 1cf29106
...@@ -4,8 +4,11 @@ export PATH=/opt/poky/1.4/sysroots/x86_64-pokysdk-linux/usr/bin/armv7a-vfp-neon- ...@@ -4,8 +4,11 @@ export PATH=/opt/poky/1.4/sysroots/x86_64-pokysdk-linux/usr/bin/armv7a-vfp-neon-
make clean make clean
make zynq_microzed_config make zynq_microzed_config
make include/autoconf.mk make include/autoconf.mk
echo "Running ezynqcfg.py for the first time - u-boot.bin length is not known yet, generating arch/arm/cpu/armv7/zynq/lowlevel.c"
ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/lowlevel.c ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/lowlevel.c
make make
echo "Running ezynqcfg.py for the second time - u-boot.bin length is known and will be used in the RBL header"
ezynq/ezynqcfg.py -c include/autoconf.mk -o boot_head.bin --uboot u-boot.bin
cat boot_head.bin u-boot.bin > boot.bin cat boot_head.bin u-boot.bin > boot.bin
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