Commit 1cf29106 authored by Andrey Filippov's avatar Andrey Filippov

added second pass to specify correct u-boot.bin image length for the RBL header

parent 0fcfd161
......@@ -376,6 +376,8 @@ class EzynqClk:
return set([pll for pll in self.pll_fdivs])
def html_list_clocks(self,html_file):
if not html_file:
return
def list_with_children(name):
result = [name]
for kid_name in self.iface_divs:
......
......@@ -47,15 +47,15 @@ DDRC_DEFS={ #not all fields are defined currently
'hpr_reg': {'OFFS': 0x008,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x3c0780f
'reg_ddrc_hpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'HPR queue transactions to be served after going critical'},
'reg_ddrc_hpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks HPR may be starved before going critical'},
'reg_ddrc_hpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number off 32x clocks HPR queue is guaranteed to be non-critical'}}},
'reg_ddrc_hpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number of 32x clocks HPR queue is guaranteed to be non-critical'}}},
'lpr_reg': {'OFFS': 0x00C,'DFLT':0x03C0780F,'RW':'RW','FIELDS':{ #0x2001001
'reg_ddrc_lpr_xact_run_length': {'r':(22,25),'d':0xF,'c':'LPR queue transactions to be served after going critical'}, # 0x8
'reg_ddrc_lpr_max_starve_x32': {'r':(11,21),'d':0xF,'c':'Number of 32x clocks LPR may be starved before going critical'}, # 0x2
'reg_ddrc_lpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number off 32x clocks LPR queue is guaranteed to be non-critical'}}}, #0x1
'reg_ddrc_lpr_min_non_critical_x32':{'r':( 0,10),'d':0xF,'c':'Number of 32x clocks LPR queue is guaranteed to be non-critical'}}}, #0x1
'wr_reg': {'OFFS': 0x010,'DFLT':0x0007F80F,'RW':'RW','FIELDS':{ #0x14001
'reg_ddrc_w_max_starve_x32': {'r':(15,25),'d':0xF,'c':'Number of 32x clocks write queue may be starved before going critical'},#0 x2 # opposite sequence from HPR,LPR
'reg_ddrc_w_xact_run_length': {'r':(11,14),'d':0xF,'c':'write queue transactions to be served after going critical'}, # 0x8
'reg_ddrc_w_min_non_critical_x32': {'r':( 0,10),'d':0xF,'c':'Number off 32x clocks write queue is guaranteed to be non-critical'}}}, # 0x2
'reg_ddrc_w_min_non_critical_x32': {'r':( 0,10),'d':0xF,'c':'Number of 32x clocks write queue is guaranteed to be non-critical'}}}, # 0x2
'dram_param_reg0': {'OFFS': 0x014,'DFLT':0x00041016,'RW':'RW','FIELDS':{ # 0x4281a
'reg_ddrc_post_selfref_gap_x32': {'r':(14,20),'d':0x10,'c':'DRAM-related, minimal time after self refresh'}, #0x10
'reg_ddrc_t_rfc_min': {'r':( 6,15),'d':0x40,'c':'Dynamic, tRFC'}, #0xa0
......
This diff is collapsed.
......@@ -107,7 +107,7 @@ CONFIG_EZYNQ_MIO_UART_1=48 # 8+4*N
#RBL header parameters
CONFIG_EZYNQ_BOOT_USERDEF= 0x1234567 # will be saved in the file header
CONFIG_EZYNQ_BOOT_OCM_OFFSET= 0x8C0 # start of OCM data relative to the flash image start >=0x8C0, 63-bytes aligned
CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0#0x30000 # number of bytes to load to the OCM memory, <= 0x30000
CONFIG_EZYNQ_BOOT_OCM_IMAGE_LENGTH= 0x30000 # number of bytes to load to the OCM memory, <= 0x30000
CONFIG_EZYNQ_START_EXEC= 0x00 # start of execution address
......
......@@ -4,8 +4,11 @@ export PATH=/opt/poky/1.4/sysroots/x86_64-pokysdk-linux/usr/bin/armv7a-vfp-neon-
make clean
make zynq_microzed_config
make include/autoconf.mk
echo "Running ezynqcfg.py for the first time - u-boot.bin length is not known yet, generating arch/arm/cpu/armv7/zynq/lowlevel.c"
ezynq/ezynqcfg.py -c include/autoconf.mk --html u-boot.html -o boot_head.bin --html-mask 0x3ff --lowlevel arch/arm/cpu/armv7/zynq/lowlevel.c
make
echo "Running ezynqcfg.py for the second time - u-boot.bin length is known and will be used in the RBL header"
ezynq/ezynqcfg.py -c include/autoconf.mk -o boot_head.bin --uboot u-boot.bin
cat boot_head.bin u-boot.bin > boot.bin
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