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Elphel
ezynq
Commits
182c3a98
Commit
182c3a98
authored
Sep 24, 2013
by
Oleg Dzhimiev
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switched to arch_cpu_init function from lowlevel_init
parent
bb274fcf
Changes
1
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1 changed file
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13 additions
and
4 deletions
+13
-4
cpu.c
u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c
+13
-4
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u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c
View file @
182c3a98
...
...
@@ -24,17 +24,23 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#ifndef CONFIG_EZYNQ
void
lowlevel_init
(
void
)
{
}
#ifndef CONFIG_EZYNQ
int
arch_cpu_init
(
void
)
{
zynq_slcr_unlock
();
/* remap DDR to zero, FILTERSTART */
writel
(
0
,
&
scu_base
->
filter_start
);
/* Device config APB, unlock the PCAP */
writel
(
0x757BDF0D
,
&
devcfg_base
->
unlock
);
writel
(
0xFFFFFFFF
,
&
devcfg_base
->
rom_shadow
);
#if (CONFIG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel
(
0
,
&
scu_base
->
filter_start
);
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel
(
0x1F
,
&
slcr_base
->
ocm_cfg
);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
...
...
@@ -45,8 +51,11 @@ void lowlevel_init(void)
writel
(
0x0
,
&
slcr_base
->
ddr_urgent_sel
);
/* Urgent write, ports S2/S3 */
writel
(
0xC
,
&
slcr_base
->
ddr_urgent
);
#endif
zynq_slcr_lock
();
return
0
;
}
#endif
void
reset_cpu
(
ulong
addr
)
...
...
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