switched to arch_cpu_init function from lowlevel_init

u-boot-tree/arch/arm/cpu/armv7/zynq/cpu.c

@@ -24,17 +24,23 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
-#ifndef CONFIG_EZYNQ
+
 void lowlevel_init(void)
+{
+}
+#ifndef CONFIG_EZYNQ
+int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
-	/* remap DDR to zero, FILTERSTART */
-	writel(0, &scu_base->filter_start);
 
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
 	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
 	writel(0x1F, &slcr_base->ocm_cfg);
 	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
@@ -45,8 +51,11 @@ void lowlevel_init(void)
 	writel(0x0, &slcr_base->ddr_urgent_sel);
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
+#endif
 
 	zynq_slcr_lock();
+
+	return 0;
 }
 #endif
 void reset_cpu(ulong addr)
@@ -62,4 +71,4 @@ void enable_caches(void)
         /* Enable D-cache. I-cache is already enabled in start.S */
         dcache_enable();
 }
-#endif
+#endif
\ No newline at end of file