added minimum files

u-boot-tree/arch/arm/dts/Makefile

+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
+dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+	exynos4210-smdkv310.dtb \
+	exynos4210-universal_c210.dtb \
+	exynos4210-trats.dtb \
+	exynos4412-trats2.dtb \
+	exynos4412-odroid.dtb
+
+dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
+	exynos5250-snow.dtb \
+	exynos5250-spring.dtb \
+	exynos5250-smdk5250.dtb \
+	exynos5420-smdk5420.dtb \
+	exynos5420-peach-pit.dtb \
+	exynos5800-peach-pi.dtb \
+	exynos5422-odroidxu3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+	rk3288-firefly.dtb \
+	rk3288-jerry.dtb \
+	rk3036-sdk.dtb
+dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
+	tegra20-medcom-wide.dtb \
+	tegra20-paz00.dtb \
+	tegra20-plutux.dtb \
+	tegra20-seaboard.dtb \
+	tegra20-tec.dtb \
+	tegra20-trimslice.dtb \
+	tegra20-ventana.dtb \
+	tegra20-whistler.dtb \
+	tegra20-colibri.dtb \
+	tegra30-apalis.dtb \
+	tegra30-beaver.dtb \
+	tegra30-cardhu.dtb \
+	tegra30-colibri.dtb \
+	tegra30-tec-ng.dtb \
+	tegra114-dalmore.dtb \
+	tegra124-jetson-tk1.dtb \
+	tegra124-nyan-big.dtb \
+	tegra124-venice2.dtb \
+	tegra210-e2220-1170.dtb \
+	tegra210-p2371-0000.dtb \
+	tegra210-p2371-2180.dtb \
+	tegra210-p2571.dtb
+
+dtb-$(CONFIG_ARCH_MVEBU) +=			\
+	armada-388-gp.dtb			\
+	armada-xp-gp.dtb
+
+dtb-$(CONFIG_ARCH_UNIPHIER) += \
+	uniphier-ph1-ld4-ref.dtb \
+	uniphier-ph1-ld6b-ref.dtb \
+	uniphier-ph1-pro4-ref.dtb \
+	uniphier-ph1-pro5-4kbox.dtb \
+	uniphier-ph1-sld3-ref.dtb \
+	uniphier-ph1-sld8-ref.dtb \
+	uniphier-proxstream2-gentil.dtb \
+	uniphier-proxstream2-vodka.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+	zynq-zc706.dtb \
+	zynq-zed.dtb \
+	zynq-zybo.dtb \
+	zynq-microzed.dtb \
+	zynq-picozed.dtb \
+	zynq-zc770-xm010.dtb \
+	zynq-zc770-xm011.dtb \
+	zynq-zc770-xm012.dtb \
+	zynq-zc770-xm013.dtb \
+	elphel393.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += \
+	zynqmp-ep108.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+
+dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
+	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_mcvevk.dtb			\
+	socfpga_cyclone5_socdk.dtb			\
+	socfpga_cyclone5_de0_nano_soc.dtb			\
+	socfpga_cyclone5_sockit.dtb			\
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
+dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
+dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
+
+dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+	ls1021a-twr.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+	fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+	fsl-ls1043a-rdb.dtb
+
+dtb-$(CONFIG_MACH_SUN4I) += \
+	sun4i-a10-a1000.dtb \
+	sun4i-a10-ba10-tvbox.dtb \
+	sun4i-a10-chuwi-v7-cw0825.dtb \
+	sun4i-a10-cubieboard.dtb \
+	sun4i-a10-gemei-g9.dtb \
+	sun4i-a10-hackberry.dtb \
+	sun4i-a10-hyundai-a7hd.dtb \
+	sun4i-a10-inet1.dtb \
+	sun4i-a10-inet-3f.dtb \
+	sun4i-a10-inet-3w.dtb \
+	sun4i-a10-inet97fv2.dtb \
+	sun4i-a10-inet9f-rev03.dtb \
+	sun4i-a10-itead-iteaduino-plus.dtb \
+	sun4i-a10-jesurun-q5.dtb \
+	sun4i-a10-marsboard.dtb \
+	sun4i-a10-mini-xplus.dtb \
+	sun4i-a10-mk802.dtb \
+	sun4i-a10-mk802ii.dtb \
+	sun4i-a10-olinuxino-lime.dtb \
+	sun4i-a10-pcduino.dtb \
+	sun4i-a10-pov-protab2-ips9.dtb
+dtb-$(CONFIG_MACH_SUN5I) += \
+	sun5i-a10s-auxtek-t003.dtb \
+	sun5i-a10s-auxtek-t004.dtb \
+	sun5i-a10s-mk802.dtb \
+	sun5i-a10s-olinuxino-micro.dtb \
+	sun5i-a10s-r7-tv-dongle.dtb \
+	sun5i-a10s-wobo-i5.dtb \
+	sun5i-a13-ampe-a76.dtb \
+	sun5i-a13-empire-electronix-d709.dtb \
+	sun5i-a13-hsg-h702.dtb \
+	sun5i-a13-inet-86vs.dtb \
+	sun5i-a13-inet-98v-rev2.dtb \
+	sun5i-a13-olinuxino.dtb \
+	sun5i-a13-olinuxino-micro.dtb \
+	sun5i-a13-q8-tablet.dtb \
+	sun5i-a13-utoo-p66.dtb \
+	sun5i-r8-chip.dtb
+dtb-$(CONFIG_MACH_SUN6I) += \
+	sun6i-a31-app4-evb1.dtb \
+	sun6i-a31-colombus.dtb \
+	sun6i-a31-hummingbird.dtb \
+	sun6i-a31-i7.dtb \
+	sun6i-a31-m9.dtb \
+	sun6i-a31-mele-a1000g-quad.dtb \
+	sun6i-a31-mixtile-loftq.dtb \
+	sun6i-a31s-cs908.dtb \
+	sun6i-a31s-primo81.dtb \
+	sun6i-a31s-sinovoip-bpi-m2.dtb
+dtb-$(CONFIG_MACH_SUN7I) += \
+	sun7i-a20-ainol-aw1.dtb \
+	sun7i-a20-bananapi.dtb \
+	sun7i-a20-bananapro.dtb \
+	sun7i-a20-cubieboard2.dtb \
+	sun7i-a20-cubietruck.dtb \
+	sun7i-a20-hummingbird.dtb \
+	sun7i-a20-i12-tvbox.dtb \
+	sun7i-a20-lamobo-r1.dtb \
+	sun7i-a20-m3.dtb \
+	sun7i-a20-m5.dtb \
+	sun7i-a20-mk808c.dtb \
+	sun7i-a20-olimex-som-evb.dtb \
+	sun7i-a20-olinuxino-lime.dtb \
+	sun7i-a20-olinuxino-lime2.dtb \
+	sun7i-a20-olinuxino-micro.dtb \
+	sun7i-a20-orangepi.dtb \
+	sun7i-a20-orangepi-mini.dtb \
+	sun7i-a20-pcduino3.dtb \
+	sun7i-a20-pcduino3-nano.dtb \
+	sun7i-a20-primo73.dtb \
+	sun7i-a20-wexler-tab7200.dtb \
+	sun7i-a20-wits-pro-a20-dkt.dtb \
+	sun7i-a20-yones-toptech-bd1078.dtb
+dtb-$(CONFIG_MACH_SUN8I_A23) += \
+	sun8i-a23-evb.dtb \
+	sun8i-a23-gt90h-v4.dtb \
+	sun8i-a23-q8-tablet.dtb
+dtb-$(CONFIG_MACH_SUN8I_A33) += \
+	sun8i-a33-ga10h-v1.1.dtb \
+	sun8i-a33-q8-tablet.dtb \
+	sun8i-a33-sinlinx-sina33.dtb
+dtb-$(CONFIG_MACH_SUN8I_A83T) += \
+	sun8i-a83t-allwinner-h8homlet-v2.dtb
+dtb-$(CONFIG_MACH_SUN8I_H3) += \
+	sun8i-h3-orangepi-pc.dtb \
+	sun8i-h3-orangepi-plus.dtb
+dtb-$(CONFIG_MACH_SUN9I) += \
+	sun9i-a80-optimus.dtb \
+	sun9i-a80-cubieboard4.dtb
+
+dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
+	vf610-colibri.dtb
+
+dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
+	k2l-evm.dtb \
+	k2e-evm.dtb \
+	k2g-evm.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb

u-boot-tree/arch/arm/dts/elphel393.dts

+/*
+ * Elphel 10393 board DTS
+ *
+ * Copyright (C) 2016 Elphel, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-3.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Elphel 10393 Board";
+	compatible = "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart0;
+                mmc0 = &sdhci0;
+                i2c0 = &i2c0;
+	};
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdhci0 {
+        u-boot,dm-pre-reloc;
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+};

u-boot-tree/arch/arm/dts/zynq-microzed.dts

+/*
+ * Xilinx MicroZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ * 
+ * Modified: Oleg Dzhimiev <oleg@elphel.com>, Elphel Inc., 2016
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq MicroZED Board";
+	compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+		spi0 = &qspi;
+                mmc0 = &sdhci0;
+	};
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+};
+
+&qspi {
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdhci0 {
+        u-boot,dm-pre-reloc;
+        status = "okay";
+};

u-boot-tree/arch/arm/dts/zynq-zc706.dts

+/*
+ * Xilinx ZC706 board DTS
+ *
+ *  Copyright (C) 2011 - 2015 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ * Modified: Oleg Dzhimiev <oleg@elphel.com>, Elphel Inc., 2016
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq ZC706 Development Board";
+        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+		spi0 = &qspi;
+                mmc0 = &sdhci0;
+	};
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+};
+
+&qspi {
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdhci0 {
+        u-boot,dm-pre-reloc;
+        status = "okay";
+};

u-boot-tree/arch/arm/dts/zynq-zed.dts

+/*
+ * Xilinx ZED board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ * 
+ * Modified: Oleg Dzhimiev <oleg@elphel.com>, Elphel Inc., 2016
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq Zed Development Board";
+	compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+		spi0 = &qspi;
+                mmc0 = &sdhci0;
+	};
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+};
+
+&qspi {
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&sdhci0 {
+        u-boot,dm-pre-reloc;
+        status = "okay";
+};

u-boot-tree/board/elphel/elphel393/Makefile

+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+$(shell touch xil_io.h)
+endif

u-boot-tree/board/elphel/elphel393/board.c

+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
+
+/* It can be done differently */
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+#endif
+
+int board_init(void)
+{
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	u32 idcode;
+
+	idcode = zynq_slcr_get_idcode();
+
+	switch (idcode) {
+	case XILINX_ZYNQ_7010:
+		fpga = fpga010;
+		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
+		break;
+	case XILINX_ZYNQ_7020:
+		fpga = fpga020;
+		break;
+	case XILINX_ZYNQ_7030:
+		fpga = fpga030;
+		break;
+	case XILINX_ZYNQ_7035:
+		fpga = fpga035;
+		break;
+	case XILINX_ZYNQ_7045:
+		fpga = fpga045;
+		break;
+	case XILINX_ZYNQ_7100:
+		fpga = fpga100;
+		break;
+	}
+#endif
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	fpga_init();
+	fpga_add(fpga_xilinx, &fpga);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_NOR:
+		setenv("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		setenv("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_NAND:
+		setenv("modeboot", "nandboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		setenv("modeboot", "jtagboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board: Elphel 10393\n");
+	return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	u32 ret = 0;
+
+#ifdef CONFIG_XILINX_AXIEMAC
+	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+						XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+	u32 txpp = 0;
+	u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	rxpp = 1;
+# endif
+	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+			txpp, rxpp);
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	int node;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	const void *blob = gd->fdt_blob;
+
+	node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+					     "memory", 7);
+	if (node == -FDT_ERR_NOTFOUND) {
+		debug("ZYNQ DRAM: Can't get memory node\n");
+		return -1;
+	}
+	addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE || size == 0) {
+		debug("ZYNQ DRAM: Can't get base address or size\n");
+		return -1;
+	}
+	gd->ram_size = size;
+#else
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+	zynq_ddrc_init();
+
+	return 0;
+}

u-boot-tree/configs/elphel393_defconfig

+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_TARGET_ELPHEL393=y
+CONFIG_DEFAULT_DEVICE_TREE="elphel393"
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPI_FLASH=n
+CONFIG_SPI_FLASH_SPANSION=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SPI_FLASH_WINBOND=n
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_QSPI=n
+CONFIG_CMD_NAND=y
+
+# i2c config is in ../include/configs/elphel393.h
+# CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=n
+
+CONFIG_CMD_SETEXPR=y
+
+CONFIG_DM_GPIO=n
+CONFIG_EFI_LOADER=n
+CONFIG_CMD_BOOTEFI=n
+
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MMC=y
+CONFIG_HUSH_PARSER=y

u-boot-tree/include/configs/elphel393.h

+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2013 Elphel
+ *
+ * Configuration for Elphel393 Board
+ * See zynq_common.h for Zynq common configs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ELPHEL393_H
+#define __CONFIG_ELPHEL393_H
+
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_ZYNQ_SDHCI
+#define CONFIG_ZYNQ_SDHCI0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_NAND_ZYNQ
+
+#ifdef CONFIG_NAND_ZYNQ
+    /*#define CONFIG_CMD_NAND*/
+    #define CONFIG_CMD_NAND_LOCK_UNLOCK
+    #define CONFIG_SYS_MAX_NAND_DEVICE 1
+    #define CONFIG_SYS_NAND_SELF_INIT
+    #define CONFIG_SYS_NAND_ONFI_DETECTION
+    #define CONFIG_MTD_DEVICE
+#endif
+
+#define CONFIG_SPL_NAND_ELPHEL393
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000 /*look-up in dts!*/
+
+/*
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x0
+#define CONFIG_SYS_NAND_U_BOOT_START	0x0
+*/
+
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_BBT
+#define CONFIG_SPL_NAND_IDS
+
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_MTD
+/*#define CONFIG_DEFAULT_DEVICE_TREE	elphel393*/
+
+/*redefined in zynq-common.h*/
+/*#undef CONFIG_CMD_NAND*/
+
+#define CONFIG_ZYNQ_I2C0
+
+#include <configs/zynq-common.h>
+
+/* Need to define it - otherwise error "FDT creation failed!"*/
+#define CONFIG_SYS_SDRAM_BASE       0
+
+#undef CONFIG_SYS_PROMPT
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_EXTRA_ENV_SETTINGS
+/*skip u-boot falcon mode*/
+#undef CONFIG_SPL_OS_BOOT
+
+#undef CONFIG_DISPLAY_BOARDINFO
+
+#include <configs/ezynq/ezynq_MT41K256M16HA107.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
+#include <configs/ezynq/ezynq_XC7Z030_1FBG484C.h>
+#include <configs/ezynq/ezynq_elphel393.h>
+
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_BOOTDELAY	1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_PROMPT		"elphel393-u-boot> "
+
+/*#define CONFIG_EZYNQ_SKIP_DDR*/
+#define CONFIG_EZYNQ_SKIP_CLK
+
+#define CONFIG_MTD_DEVICE
+
+/* UBI support in full U-Boot */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDIDS_DEFAULT  "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:1m(u-boot-spl),"   \
+                         "4m(u-boot)," \
+                         "1m(device-tree)," \
+                         "16m(kernel)," \
+                         "256m(rootfs)," \
+                         "256m(rootfs)"
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0e:64:10:00:00\0"	\
+	"kernel_image=uImage\0"	\
+	"ramdisk_image=uramdisk.image.gz\0"	\
+	"devicetree_image=devicetree.dtb\0"	\
+	"bitstream_image=system.bit.bin\0"	\
+	"boot_image=BOOT.bin\0"	\
+	"loadbit_addr=0x100000\0"	\
+	"loadbootenv_addr=0x2000000\0" \
+	"kernel_size=0x800000\0"	\
+	"devicetree_size=0x100000\0"	\
+	"ramdisk_size=0x1E00000\0"	\
+	"boot_size=0xF00000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from SD ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"norboot=echo Copying Linux from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
+		"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x3000000 0x100000 ${kernel_size} && " \
+		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"uenvboot=" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi; " \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi\0" \
+	"sdboot=if mmcinfo; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from SD to RAM... && " \
+			"fatload mmc 0 0x4F00000 ${kernel_image} && " \
+			"fatload mmc 0 0x4E00000 ${devicetree_image} && " \
+			"bootm 0x4F00000 - 0x4E00000; " \
+		"fi\0" \
+	"usbboot=if usb start; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from USB to RAM... && " \
+			"fatload usb 0 0x3000000 ${kernel_image} && " \
+			"fatload usb 0 0x2A00000 ${devicetree_image} && " \
+			"fatload usb 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3000000 0x2000000 0x2A00000; " \
+		"fi\0" \
+	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
+		"nand read 0x4F00000 0x600000 ${kernel_size} && " \
+		"nand read 0x4E00000 0x500000 ${devicetree_size} && " \
+		"bootm 0x4F00000 - 0x4E00000\0" \
+	"devboot= echo Copying Linux from SD to RAM... && " \
+		"fatload mmc 0 0x4F00000 ${kernel_image} && " \
+		" echo Copying Device Tree from NAND flash to RAM && " \
+		"nand read 0x4E00000 0x500000 ${devicetree_size} && " \
+		"bootm 0x4F00000 - 0x4E00000\0" \
+        "nandboot2=echo NAND boot 2... ; " \
+                "mtd default; " \
+                "mtd4=0; " \
+                "ubi part nand0,4; " \
+                "if ubi check elphel393-rootfs; then " \
+                    "mtd4=1; " \
+                "fi; " \
+                "mtd5=0; " \
+                "ubi part nand0,5; " \
+                "if ubi check elphel393-rootfs; then " \
+                    "mtd5=1; " \
+                "fi; " \
+                "i2c read 68 4 1 ${loadbootenv_addr}; " \
+                "setexpr.b bootsrc *${loadbootenv_addr} \\\\& 0x80; " \
+                "setexpr bootsrc ${bootsrc} / 0x80; " \
+                "setexpr bootsrc ${bootsrc} \\\\& ${mtd4}; " \
+                "setexpr bootsrc ${bootsrc} \\\\& ${mtd5}; " \
+                "setexpr bootsrc ${bootsrc} \\\\^ ${mtd5}; " \
+                "if test ${bootsrc} -eq 1; then " \
+                    "echo Booting from mtd4!; " \
+                "else " \
+                    "echo Booting from mtd5!; " \
+                "fi\0" \
+	"jtagboot=echo TFTPing Linux to RAM... && " \
+		"tftpboot 0x3000000 ${kernel_image} && " \
+		"tftpboot 0x2A00000 ${devicetree_image} && " \
+		"tftpboot 0x2000000 ${ramdisk_image} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x100000 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+		"nand read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_sdboot=echo Copying Image from SD to RAM... && " \
+		"fatload mmc 0 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_jtagboot=echo TFTPing Image to RAM... && " \
+		"tftpboot 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0"
+
+/*  */
+#endif /* __CONFIG_ELPHEL393_H */

u-boot-tree/include/configs/ezynq/ezynq_MT41J128M16HA15E.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Micron MT41K256M16HA107 DDR3L memory
+ * backward compatible to Micron MT41K256M16RE125 (used in microzed, will keep settings initially)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_EZYNQ_MT41J128M16HA15E_H
+#define __CONFIG_EZYNQ_MT41J128M16HA15E_H
+
+#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41J128M16HA15E /* Memory part number  (currently not used - derive some parameters later) */
+/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
+#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
+
+#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */
+#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */
+#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */
+#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       16  /* Memory chip bus width (not yet used) */
+#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
+#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RP             13.1 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
+#define CONFIG_EZYNQ_DDR_DS_T_RC             48.75/* Activate to Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        35.0 /* Minimal Row Active time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_FAW            40.0 /* Minimal running window for 4 page activates (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
+#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
+#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
+#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
+#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
+#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
+#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */
+#define CONFIG_EZYNQ_DDR_DS_WLMRD            40   /* Write leveling : time to the first DQS rising edge (cycles). */
+#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKE             7.5 /* CKE min pulse width (ns). 7.5  */
+#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
+#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
+#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
+
+
+#endif /* __CONFIG_EZYNQ_MT41J128M16HA15E_H */

u-boot-tree/include/configs/ezynq/ezynq_MT41J256M8HX15E.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Micron MT41J256M8HX15E DDR3 memory
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_EZYNQ_MT41J256M8HX15E_H
+#define __CONFIG_EZYNQ_MT41J256M8HX15E_H
+
+#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41J256M8HX15E /* Memory part number  (currently not used - derive some parameters later) */
+/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
+#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
+
+#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */
+#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */
+#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */
+#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       8  /* Memory chip bus width (not yet used) */
+#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.125 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
+#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RP             13.125 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
+#define CONFIG_EZYNQ_DDR_DS_T_RC             49.5/* Activate to Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        36.0 /* Minimal Row Active time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_FAW            30.0 /* Minimal running window for 4 page activates (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
+#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
+#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
+#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
+#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
+#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
+#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */
+#define CONFIG_EZYNQ_DDR_DS_T_WLMRD          40.0 /* Write leveling : time to the first DQS rising edge (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKE             7.5 /* CKE min pulse width (ns). 5.625  */
+#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
+#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
+#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
+
+
+#endif /* __CONFIG_EZYNQ_MT41J256M8HX15E_H */

u-boot-tree/include/configs/ezynq/ezynq_MT41K256M16HA107.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Micron MT41K256M16HA107 DDR3L memory
+ * backward compatible to Micron MT41K256M16RE125 (used in microzed, will keep settings initially)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_EZYNQ_MT41K256M16RE125_H
+#define __CONFIG_EZYNQ_MT41K256M16RE125_H
+
+#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41K256M16HA107 /* Memory part number  (currently not used - derive some parameters later) */
+/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
+#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3L  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
+
+#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */
+#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */
+#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */
+#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       16  /* Memory chip bus width (not yet used) */
+#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
+#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RP             13.1 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
+#define CONFIG_EZYNQ_DDR_DS_T_RC             48.75/* Activate to Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        35.0 /* Minimal Row Active time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_FAW            40.0 /* Minimal running window for 4 page activates (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
+#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
+#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
+#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
+#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
+#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
+#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */
+#define CONFIG_EZYNQ_DDR_DS_WLMRD            40   /* Write leveling : time to the first DQS rising edge (cycles). */
+#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKE             5.625 /* CKE min pulse width (ns). 7.5  */
+#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
+#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
+#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
+
+
+#endif /* __CONFIG_EZYNQ_MT41K256M16RE125_H */

u-boot-tree/include/configs/ezynq/ezynq_MT41K256M16RE125.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Micron MT41K256M16RE125 DDR3L memory
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_EZYNQ_MT41K256M16RE125_H
+#define __CONFIG_EZYNQ_MT41K256M16RE125_H
+
+#define CONFIG_EZYNQ_DDR_DS_PARTNO           MT41K256M16RE125 /* Memory part number  (currently not used - derive some parameters later) */
+/* CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE will be redefined to DDR3 as Zynq is slow with DDR3 */
+#define CONFIG_EZYNQ_DDR_DS_MEMORY_TYPE      DDR3L  /* DDR memory type: DDR3 (1.5V), DDR3L (1.35V), DDR2 (1.8V), LPDDR2 (1.2V) */
+
+#define CONFIG_EZYNQ_DDR_DS_BANK_ADDR_COUNT   3  /* Number of DDR banks */
+#define CONFIG_EZYNQ_DDR_DS_ROW_ADDR_COUNT   15  /* Number of DDR Row Address bits */
+#define CONFIG_EZYNQ_DDR_DS_COL_ADDR_COUNT   10  /* Number of DDR Column address bits */
+#define CONFIG_EZYNQ_DDR_DS_DRAM_WIDTH       16  /* Memory chip bus width (not yet used) */
+#define CONFIG_EZYNQ_DDR_DS_RCD              7   /* DESCRIPTION':'RAS to CAS delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RCD           13.1 /* Activate to internal Read or Write (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RCD automatically */
+#define CONFIG_EZYNQ_DDR_DS_RP               7   /* Row Precharge time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RP             13.1 /* Precharge command period (ns).  May be used to calculate CONFIG_EZYNQ_DDR_DS_RP automatically, */
+#define CONFIG_EZYNQ_DDR_DS_T_RC             48.75/* Activate to Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RAS_MIN        35.0 /* Minimal Row Active time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_FAW            40.0 /* Minimal running window for 4 page activates (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_RFC           300.0 /* Minimal Refresh-to-Activate or Refresh command period (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_WR             15.0 /* Write recovery time (ns) */
+#define CONFIG_EZYNQ_DDR_DS_T_REFI_US         7.8 /* Maximal average periodic refresh, microseconds. Will be automatically reduced if high temperature option is selected */
+#define CONFIG_EZYNQ_DDR_DS_RTP               4 /* Minimal Read-to-Precharge time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_RTP/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_RTP             7.5 /* Minimal Read-to-Precharge time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_RTP */
+#define CONFIG_EZYNQ_DDR_DS_WTR               4   /* Minimal Write-to-Read time (in tCK). Will use max of this and CONFIG_EZYNQ_DDR_DS_T_WTR/tCK */
+#define CONFIG_EZYNQ_DDR_DS_T_WTR             7.5 /* Minimal Write-to-Read time  (ns). Will use max of this divided by tCK and CONFIG_EZYNQ_DDR_DS_WTR */
+#define CONFIG_EZYNQ_DDR_DS_XP                4   /* Minimal time from power down (DLL on) to any operation (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_DQSCK_MAX       5.5 /* LPDDR2 only. DQS output access time from CK (ns). Used for LPDDR2 */
+#define CONFIG_EZYNQ_DDR_DS_CCD               5   /* DESCRIPTION':'CAS-to-CAS command delay (in tCK) (4 in Micron DS) */
+#define CONFIG_EZYNQ_DDR_DS_RRD               6   /* ACTIVATE-to-ACTIVATE minimal command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_RRD            10.0 /* ACTIVATE-to-ACTIVATE minimal command period (ns). May be used to calculate CONFIG_EZYNQ_DDR_DS_RRD automatically */
+#define CONFIG_EZYNQ_DDR_DS_MRD               4   /* MODE REGISTER SET command period (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_MOD              12   /* MODE REGISTER SET update delay (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_MOD            15.0 /* MODE REGISTER SET update delay  (ns). */
+#define CONFIG_EZYNQ_DDR_DS_WLMRD            40   /* Write leveling : time to the first DQS rising edge (cycles). */
+#define CONFIG_EZYNQ_DDR_DS_CKE               3   /* CKE min pulse width (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKE             5.625 /* CKE min pulse width (ns). 7.5  */
+#define CONFIG_EZYNQ_DDR_DS_CKSRE             5   /* Keep valid clock after self refresh/power down entry (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRE          10.0 /* Keep valid clock after self refresh/power down entry (ns). */
+#define CONFIG_EZYNQ_DDR_DS_CKSRX             5   /* Valid clock before self refresh, power down or reset exit (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_T_CKSRX          10.0 /* Valid clock before self refresh, power down or reset exit (ns). */
+#define CONFIG_EZYNQ_DDR_DS_ZQCS             64   /* ZQCS command: short calibration time (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_ZQCL            512   /* ZQCL command: long calibration time, including init (in tCK) */
+#define CONFIG_EZYNQ_DDR_DS_INIT2             5   /* LPDDR2 only: tINIT2 (in tCK): clock stable before CKE high */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT4_US        1.0 /* LPDDR2 only: tINIT4 (in us)- minimal idle time after RESET command. */
+#define CONFIG_EZYNQ_DDR_DS_T_INIT5_US       10.0 /* LPDDR2 only: tINIT5 (in us)- maximal duration of device auto initialization. */
+#define CONFIG_EZYNQ_DDR_DS_T_ZQINIT_US       1.0 /* LPDDR2 only: tZQINIT (in us)- ZQ initial calibration time. */
+
+
+#endif /* __CONFIG_EZYNQ_MT41K256M16RE125_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z010_1CLG400.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Xilinx XC7Z010_1CLG400 SoC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_XC7Z010_1CLG400_H
+#define __CONFIG_XC7Z010_1CLG400_H
+
+/* datasheet data for specific speed grades */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
+
+/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0
+#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504
+#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495
+#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520
+#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835
+#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465
+#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480
+#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550
+#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0
+/* Sorry for propOgation - this is how it is called in the tools */
+#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
+
+
+#endif /* __CONFIG_XC7Z010_1CLG400_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z020_1CLG484.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Xilinx XC7Z020_1CLG484 SoC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_XC7Z020_1CLG484_H
+#define __CONFIG_XC7Z020_1CLG484_H
+
+/* datasheet data for specific speed grades */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
+
+/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0
+#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504
+#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495
+#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520
+#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835
+#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465
+#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480
+#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550
+#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0
+/* Sorry for propOgation - this is how it is called in the tools */
+#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
+
+
+#endif /* __CONFIG_XC7Z020_1CLG484_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z030_1FBG484C.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Xilinx XC7Z030_1FBG484C SoC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_XC7Z030_1FBG484C_H
+#define __CONFIG_XC7Z030_1FBG484C_H
+
+/* datasheet data for specific speed grades */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   800.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_1_MBPS   1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_2_MBPS   1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3L_MAX_3_MBPS   1066.0 /* Maximal DDR3L performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
+
+/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */
+/* TODO: not yet modified from XC7Z010_1CLG400 */
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0
+#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504
+#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495
+#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520
+#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835
+#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465
+#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480
+#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550
+#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0
+/* Sorry for propOgation - this is how it is called in the tools */
+#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
+
+
+#endif /* __CONFIG_XC7Z030_1FBG484C_H */

u-boot-tree/include/configs/ezynq/ezynq_XC7Z045_2FFG900C.h

+ /*
+ * (C) Copyright 2013 Elphel, Inc.
+ *
+ * Configuration for ezynq for Xilinx XC7Z045_2FFG900C SoC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_XC7Z045_2FFG900C_H
+#define __CONFIG_XC7Z045_2FFG900C_H
+
+/* datasheet data for specific speed grades */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_1_MHZ     1600.0 /* Maximal PLL clock frequency for speed grade 1 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_2_MHZ     1800.0 /* Maximal PLL clock frequency for speed grade 2 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_PLL_MAX_3_MHZ     2000.0 /* Maximal PLL clock frequency for speed grade 3 (MHz) */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_1_MHZ   667.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_2_MHZ   733.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM621_MAX_3_MHZ  1000.0 /* Maximal ARM clk_6x4x in 621 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_1_MHZ   533.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 1, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_2_MHZ   600.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 2, MHz */
+#define CONFIG_EZYNQ_CLK_DS_ARM421_MAX_3_MHZ   710.0 /* Maximal ARM clk_6x4x in 421 mode for speed grade 3, MHz */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_1_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_2_MBPS   1066.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR3_MAX_3_MBPS   1333.0 /* Maximal DDR3 performance in Mb/s - twice clock frequency (MHz). Speed grade 3 */
+#define CONFIG_EZYNQ_CLK_DS_DDRX_MAX_X_MBPS    800.0 /* Maximal DDR3L, DDR2, LPDDR2 performance in Mb/s - twice clock frequency (MHz). All speed grades */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_1_MHZ   355.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 1 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_2_MHZ   408.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 2 */
+#define CONFIG_EZYNQ_CLK_DS_DDR_2X_MAX_3_MHZ   444.0 /* Maximal DDR_2X clock frequency (MHz) for speed grade 3 */
+
+/*  SoC  parameters to set phases manually (or as a starting point for automatic) Not yet processed */
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_0        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_1        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_2        0.0
+#define CONFIG_EZYNQ_DDR_DQS_TO_CLK_DELAY_3        0.0
+#define CONFIG_EZYNQ_DDR_DQS_0_PACKAGE_LENGTH      504
+#define CONFIG_EZYNQ_DDR_DQS_1_PACKAGE_LENGTH      495
+#define CONFIG_EZYNQ_DDR_DQS_2_PACKAGE_LENGTH      520
+#define CONFIG_EZYNQ_DDR_DQS_3_PACKAGE_LENGTH      835
+#define CONFIG_EZYNQ_DDR_DQ_0_PACKAGE_LENGTH       465
+#define CONFIG_EZYNQ_DDR_DQ_1_PACKAGE_LENGTH       480
+#define CONFIG_EZYNQ_DDR_DQ_2_PACKAGE_LENGTH       550
+#define CONFIG_EZYNQ_DDR_DQ_3_PACKAGE_LENGTH       780
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PACKAGE_LENGTH    470.0
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PACKAGE_LENGTH    470.0
+/* Sorry for propOgation - this is how it is called in the tools */
+#define CONFIG_EZYNQ_DDR_DQS_0_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_1_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_2_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQS_3_PROPOGATION_DELAY   160
+#define CONFIG_EZYNQ_DDR_DQ_0_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_1_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_2_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_DQ_3_PROPOGATION_DELAY    160
+#define CONFIG_EZYNQ_DDR_CLOCK_0_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_1_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_2_PROPOGATION_DELAY 160
+#define CONFIG_EZYNQ_DDR_CLOCK_3_PROPOGATION_DELAY 160
+
+
+#endif /* __CONFIG_XC7Z045_2FFG900C */

u-boot-tree/include/configs/zynq_microzed.h

+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+
+#define CONFIG_NAND_ZYNQ
+
+/*#define CONFIG_DEFAULT_DEVICE_TREE	zynq-microzed*/
+
+/*redefined in zynq-common.h*/
+#undef CONFIG_CMD_NAND
+
+#include <configs/zynq-common.h>
+#undef CONFIG_SYS_PROMPT
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_EXTRA_ENV_SETTINGS
+/*skip u-boot falcon mode*/
+#undef CONFIG_SPL_OS_BOOT
+
+#include <configs/ezynq/ezynq_MT41K256M16RE125.h>  /* should be before ezynq_microzed.h as it overwrites DDR3L with DDR3 */
+#include <configs/ezynq/ezynq_XC7Z010_1CLG400.h>
+#include <configs/ezynq/ezynq_microzed.h>
+
+#define CONFIG_BOOTDELAY	1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_PROMPT		"microzed-u-boot> "
+
+/*#define CONFIG_EZYNQ_SKIP_DDR*/
+#define CONFIG_EZYNQ_SKIP_CLK
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0a:35:00:01:22\0"	\
+	"kernel_image=uImage\0"	\
+	"ramdisk_image=uramdisk.image.gz\0"	\
+	"devicetree_image=devicetree.dtb\0"	\
+	"bitstream_image=system.bit.bin\0"	\
+	"boot_image=BOOT.bin\0"	\
+	"loadbit_addr=0x100000\0"	\
+	"loadbootenv_addr=0x2000000\0" \
+	"kernel_size=0x500000\0"	\
+	"devicetree_size=0x20000\0"	\
+	"ramdisk_size=0x5E0000\0"	\
+	"boot_size=0xF00000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from SD ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"norboot=echo Copying Linux from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
+		"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x3000000 0x100000 ${kernel_size} && " \
+		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"uenvboot=" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi; " \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi\0" \
+	"sdboot=if mmcinfo; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from SD to RAM... && " \
+			"fatload mmc 0 0x4F00000 ${kernel_image} && " \
+			"fatload mmc 0 0x4E00000 ${devicetree_image} && " \
+			"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x4F00000 0x2000000 0x4E00000; " \
+		"fi\0" \
+	"usbboot=if usb start; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from USB to RAM... && " \
+			"fatload usb 0 0x3000000 ${kernel_image} && " \
+			"fatload usb 0 0x2A00000 ${devicetree_image} && " \
+			"fatload usb 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3000000 0x2000000 0x2A00000; " \
+		"fi\0" \
+	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
+		"nand read 0x3000000 0x100000 ${kernel_size} && " \
+		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"jtagboot=echo TFTPing Linux to RAM... && " \
+		"tftpboot 0x3000000 ${kernel_image} && " \
+		"tftpboot 0x2A00000 ${devicetree_image} && " \
+		"tftpboot 0x2000000 ${ramdisk_image} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x100000 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+		"nand read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_sdboot=echo Copying Image from SD to RAM... && " \
+		"fatload mmc 0 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_jtagboot=echo TFTPing Image to RAM... && " \
+		"tftpboot 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0"
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */

u-boot-tree/include/configs/zynq_zc706.h

+/*
+ * (C) Copyright 2012 Xilinx
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq_common.h for Zynq common configs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC706_H
+#define __CONFIG_ZYNQ_ZC706_H
+
+#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+/*#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc706*/
+
+#include <configs/zynq-common.h>
+#undef CONFIG_SYS_PROMPT
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_EXTRA_ENV_SETTINGS
+/*skip u-boot falcon mode*/
+#undef CONFIG_SPL_OS_BOOT
+
+#include <configs/ezynq/ezynq_MT41J256M8HX15E.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
+#include <configs/ezynq/ezynq_XC7Z045_2FFG900C.h>
+#include <configs/ezynq/ezynq_zc706.h>
+
+#define CONFIG_BOOTDELAY	1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_PROMPT		"zc706-u-boot> "
+
+/*#define CONFIG_EZYNQ_SKIP_DDR*/
+#define CONFIG_EZYNQ_SKIP_CLK
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0a:35:00:01:22\0"	\
+	"kernel_image=uImage\0"	\
+	"ramdisk_image=uramdisk.image.gz\0"	\
+	"devicetree_image=devicetree.dtb\0"	\
+	"bitstream_image=system.bit.bin\0"	\
+	"boot_image=BOOT.bin\0"	\
+	"loadbit_addr=0x100000\0"	\
+	"loadbootenv_addr=0x2000000\0" \
+	"kernel_size=0x500000\0"	\
+	"devicetree_size=0x20000\0"	\
+	"ramdisk_size=0x5E0000\0"	\
+	"boot_size=0xF00000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from SD ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"norboot=echo Copying Linux from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
+		"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x3000000 0x100000 ${kernel_size} && " \
+		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"uenvboot=" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi; " \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi\0" \
+	"sdboot=if mmcinfo; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from SD to RAM... && " \
+			"fatload mmc 0 0x3F00000 ${kernel_image} && " \
+			"fatload mmc 0 0x3E00000 ${devicetree_image} && " \
+			"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3F00000 0x2000000 0x3E00000; " \
+		"fi\0" \
+	"usbboot=if usb start; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from USB to RAM... && " \
+			"fatload usb 0 0x3000000 ${kernel_image} && " \
+			"fatload usb 0 0x2A00000 ${devicetree_image} && " \
+			"fatload usb 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3000000 0x2000000 0x2A00000; " \
+		"fi\0" \
+	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
+		"nand read 0x3000000 0x100000 ${kernel_size} && " \
+		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"jtagboot=echo TFTPing Linux to RAM... && " \
+		"tftpboot 0x3000000 ${kernel_image} && " \
+		"tftpboot 0x2A00000 ${devicetree_image} && " \
+		"tftpboot 0x2000000 ${ramdisk_image} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x100000 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+		"nand read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_sdboot=echo Copying Image from SD to RAM... && " \
+		"fatload mmc 0 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_jtagboot=echo TFTPing Image to RAM... && " \
+		"tftpboot 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0"
+
+/*  */
+#endif /* __CONFIG_ZYNQ_ZC706_H */

u-boot-tree/include/configs/zynq_zed.h

+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_USB
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_QSPI
+
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+/*#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed*/
+
+#include <configs/zynq-common.h>
+#undef CONFIG_SYS_PROMPT
+#undef CONFIG_BOOTDELAY
+#undef CONFIG_EXTRA_ENV_SETTINGS
+/*skip u-boot falcon mode*/
+#undef CONFIG_SPL_OS_BOOT
+
+#include <configs/ezynq/ezynq_MT41J128M16HA15E.h>  /* should be before zed_ezynq.h as it overwrites DDR3L with DDR3 */
+#include <configs/ezynq/ezynq_XC7Z020_1CLG484.h>
+#include <configs/ezynq/ezynq_zed.h>
+
+#define CONFIG_BOOTDELAY	1 /* -1 to Disable autoboot */
+#define CONFIG_SYS_PROMPT		"zed-u-boot> "
+
+/*#define CONFIG_EZYNQ_SKIP_DDR*/
+#define CONFIG_EZYNQ_SKIP_CLK
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:0a:35:00:01:22\0"	\
+	"kernel_image=uImage\0"	\
+	"ramdisk_image=uramdisk.image.gz\0"	\
+	"devicetree_image=devicetree.dtb\0"	\
+	"bitstream_image=system.bit.bin\0"	\
+	"boot_image=BOOT.bin\0"	\
+	"loadbit_addr=0x100000\0"	\
+	"loadbootenv_addr=0x2000000\0" \
+	"kernel_size=0x500000\0"	\
+	"devicetree_size=0x20000\0"	\
+	"ramdisk_size=0x5E0000\0"	\
+	"boot_size=0xF00000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from SD ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"mmc_loadbit_fat=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"norboot=echo Copying Linux from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x3000000 ${kernel_size} && " \
+		"cp.b 0xE2600000 0x2A00000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"cp.b 0xE2620000 0x2000000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x3000000 0x100000 ${kernel_size} && " \
+		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"uenvboot=" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi; " \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi\0" \
+	"sdboot=if mmcinfo; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from SD to RAM... && " \
+			"fatload mmc 0 0x3F00000 ${kernel_image} && " \
+			"fatload mmc 0 0x3E00000 ${devicetree_image} && " \
+			"fatload mmc 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3F00000 0x2000000 0x3E00000; " \
+		"fi\0" \
+	"usbboot=if usb start; then " \
+			"run uenvboot; " \
+			"echo Copying Linux from USB to RAM... && " \
+			"fatload usb 0 0x3000000 ${kernel_image} && " \
+			"fatload usb 0 0x2A00000 ${devicetree_image} && " \
+			"fatload usb 0 0x2000000 ${ramdisk_image} && " \
+			"bootm 0x3000000 0x2000000 0x2A00000; " \
+		"fi\0" \
+	"nandboot=echo Copying Linux from NAND flash to RAM... && " \
+		"nand read 0x3000000 0x100000 ${kernel_size} && " \
+		"nand read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"nand read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"jtagboot=echo TFTPing Linux to RAM... && " \
+		"tftpboot 0x3000000 ${kernel_image} && " \
+		"tftpboot 0x2A00000 ${devicetree_image} && " \
+		"tftpboot 0x2000000 ${ramdisk_image} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_norboot=echo Copying Image from NOR flash to RAM... && " \
+		"cp.b 0xE2100000 0x100000 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_nandboot=echo Copying Image from NAND flash to RAM... && " \
+		"nand read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_qspiboot=echo Copying Image from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x100000 0x0 ${boot_size} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_sdboot=echo Copying Image from SD to RAM... && " \
+		"fatload mmc 0 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"rsa_jtagboot=echo TFTPing Image to RAM... && " \
+		"tftpboot 0x100000 ${boot_image} && " \
+		"zynqrsa 0x100000 && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0"
+
+#endif /* __CONFIG_ZYNQ_ZED_H */