Commit 057cb78b authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
Browse files

tmp commented out early init

parent a79a87a3

ezynq_uboot.py

+2 −2
Original line number Diff line number Diff line
@@ -763,7 +763,7 @@ int arch_cpu_init(void) 
            self.cfile+='\tuart_wait_tx_fifo_empty(); /* Second time - for some reason 1 wait sometimes fails after LAST_PRINT_DEBUG */\n'

             

        self.cfile+='''/* set up the CPU clk clock frequency in the global data struct */

	zynq_clk_early_init();

	//zynq_clk_early_init();

'''

             

#LOCK_SLCR