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Elphel
ezynq
Commits
057cb78b
Commit
057cb78b
authored
Dec 22, 2018
by
Oleg Dzhimiev
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tmp commented out early init
parent
a79a87a3
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ezynq_uboot.py
ezynq_uboot.py
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ezynq_uboot.py
View file @
057cb78b
...
...
@@ -763,7 +763,7 @@ int arch_cpu_init(void)
self
.
cfile
+=
'
\t
uart_wait_tx_fifo_empty(); /* Second time - for some reason 1 wait sometimes fails after LAST_PRINT_DEBUG */
\n
'
self
.
cfile
+=
'''/* set up the CPU clk clock frequency in the global data struct */
zynq_clk_early_init();
//
zynq_clk_early_init();
'''
#LOCK_SLCR
...
...
@@ -785,4 +785,4 @@ int arch_cpu_init(void)
c_out_file
=
open
(
cname
,
'w'
)
c_out_file
.
write
(
self
.
cfile
)
c_out_file
.
close
()
\ No newline at end of file
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