Commit 01e77ff5 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Working on UART support for dumping registers before DDR initialization

parent 9cfda386

ezynq_clk.py

+24 −21
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ class EzynqClk: 
            return

        html_file.write('<h2>Clock configuration parameters</h2>\n')

        self.features.html_list_features(html_file)

    def get_clocks(self):

        return self.iface_divs

    def calculate_dependent_pars(self):

        speed_grade=self.features.get_par_value_or_default("SPEED_GRADE")

        ddr_type=self.ddr_type
@@ -408,6 +410,8 @@ class EzynqClk: 
        html_file.write('</table>')

    def get_ddr_mhz(self):

        return self.f_in*self.pll_fdivs[self.iface_divs['DDR']['PLL']]/self.iface_divs['DDR']['DIV']

    def get_uart_mhz(self):

        return self.iface_divs['UART']['FREQ']



    def get_new_register_sets(self):

        return self.clk_register_set.get_register_sets(True,True)
@@ -417,37 +421,22 @@ class EzynqClk: 
        clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state

        if unlock_needed:

            self.slcr_unlock()

            _ = clk_register_set.get_register_sets(True,True) # close previous register settings

            clk_register_set.flush() # close previous register settings

# Bypass used PLL-s - stage 1 of PLL setup     

        self.clocks_pll_bypass(force=False,warn=False)

        _ = clk_register_set.get_register_sets(True,True) # close previous register settings

        clk_register_set.flush() # close previous register settings

# Turn on PLL reset and program feedback -  stage 2 of PLL setup     

        self.clocks_pll_reset_and_fdiv(force=False,warn=False)

        _ = clk_register_set.get_register_sets(True,True) # close previous register settings

        clk_register_set.flush() # close previous register settings

# Configure PLL parameters -  stage 3 of PLL setup     

        self.clocks_pll_conf(force=False,warn=False)

        _ = clk_register_set.get_register_sets(True,True) # close previous register settings

        clk_register_set.flush() # close previous register settings

# Release reset of the PLLs (let them start) -  stage 4 of PLL setup     

        self.clocks_pll_start(force=False,warn=False)

        _ = clk_register_set.get_register_sets(True,True) # close previous register settings

        clk_register_set.flush() # close previous register settings

# stage 5 of clocks setup

        self.clocks_program(force=False,warn=False)

  

# #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?                

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)        

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)        

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),

#                                                               ('enable',1),

#                                                               ('nref_opt1',0),

#                                                               ('nref_opt2',0),

#                                                               ('nref_opt4',1),

#                                                               ('pref_opt2',0),

#                                                               ('update_control',0)),force,warn)        

    

    

        return self.get_new_register_sets()



#Unlock SLCR (if the code is running after RBL) - stage 0 of PLL setup     

    def slcr_unlock(self):
@@ -528,6 +517,17 @@ class EzynqClk: 
    def clocks_pll_bypass_off(self,current_reg_sets,force=False,warn=False):

        clk_register_set=self.clk_register_set

        clk_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state

# add wait for DCI calibration DONE

#        ddriob_register_set.wait_reg_field_values('ddriob_dci_status',('done',1), True, warn)

        bits=[]

        if 'ARM' in self.pll_fdivs:

            bits.append(('arm_pll_lock',1))

        if 'DDR' in self.pll_fdivs:

            bits.append(('ddr_pll_lock',1))

        if  'IO' in self.pll_fdivs:

            bits.append(('io_pll_lock',1))

        

        clk_register_set.wait_reg_field_values('pll_status',tuple(bits), True, warn)



        if 'DDR' in self.pll_fdivs:

            clk_register_set.set_bitfields('ddr_pll_ctrl',(('pll_bypass_force',  0),
@@ -538,6 +538,8 @@ class EzynqClk: 
        if 'ARM' in self.pll_fdivs:

            clk_register_set.set_bitfields('arm_pll_ctrl',(('pll_bypass_force',  0),

                                                           ('pll_bypass_qual',   0)),force,warn)

        return self.get_new_register_sets()





#clocks setup 

    def clocks_program(self,force=False,warn=False):
@@ -869,6 +871,7 @@ class EzynqClk: 


# reg  uart_clk_ctrl, offs=0x154 dflt:0x3f03 actual: 0xa02

        if 'UART' in self.iface_divs:

            print self.iface_divs['UART']

            if self.iface_divs['UART']['PLL']=='ARM':     

                uart_srcsel= 2

            elif self.iface_divs['UART']['PLL']=='DDR':

ezynq_ddr.py

+7 −20
Original line number Diff line number Diff line
@@ -253,6 +253,8 @@ class EzynqDDR: 
        ddrc_register_set=self.ddrc_register_set

        ddrc_register_set.set_initial_state(current_reg_sets, True)

        ddrc_register_set.set_bitfields('ddrc_ctrl',(('reg_ddrc_soft_rstb', 0x1)),force,warn)

        # add wait for DDR ready

        ddrc_register_set.wait_reg_field_values('mode_sts_reg',('ddrc_reg_operating_mode',0), False, warn)

        return ddrc_register_set.get_register_sets(True,True)

        

    def ddr_init_memory(self,current_reg_sets,force=False,warn=False):
@@ -1328,9 +1330,9 @@ class EzynqDDR: 
        ddriob_register_set=self.ddriob_register_set

        ddriob_register_set.set_initial_state(current_reg_sets, True)# start from the current registers state

        ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)        

        _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

        ddriob_register_set.flush() # close previous register settings

        ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)        

        _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

        ddriob_register_set.flush()# close previous register settings

        ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),

                                                              ('enable',1),

                                                              ('nref_opt1',0),
@@ -1338,6 +1340,9 @@ class EzynqDDR: 
                                                              ('nref_opt4',1),

                                                              ('pref_opt2',0),

                                                              ('update_control',0)),force,warn)

# add wait for DCI calibration DONE

        ddriob_register_set.wait_reg_field_values('ddriob_dci_status',('done',1), True, warn)



        return ddriob_register_set.get_register_sets(True,True) # close previous register settings, return new result
@@ -1443,24 +1448,6 @@ class EzynqDDR: 
                                                        ('slew_p', self.features.get_par_value('BIDIR_SLEW_POS')),

                                                        ('drive_n',self.features.get_par_value('BIDIR_DRIVE_NEG')),

                                                        ('drive_p',self.features.get_par_value('BIDIR_DRIVE_POS'))),force,warn) #0xf9861c

#             

# #Trying toggle feature (but actually for now it can be left in reset state - is this on/off/on needed?                

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

# #        ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('vrn_out',0),force,warn) # default value shows 1, actual settings - 0  (first time only?)

# #

# # Do in u-boot. When moving - use UG585 table 10-7 to set options

# #      

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',1),force,warn)        

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', ('reset',0),force,warn)        

#         _ = ddriob_register_set.get_register_sets(True,True) # close previous register settings

#         ddriob_register_set.set_bitfields('ddriob_dci_ctrl', (('reset', 1),

#                                                               ('enable',1),

#                                                               ('nref_opt1',0),

#                                                               ('nref_opt2',0),

#                                                               ('nref_opt4',1),

#                                                               ('pref_opt2',0),

#                                                               ('update_control',0)),force,warn)        

  

#TODO: Remove?

ezynq_ddrc_defs.py

+1 −1
Original line number Diff line number Diff line
@@ -194,7 +194,7 @@ DDRC_DEFS={ #not all fields are defined currently 
                  'reg_phy_rdc_we_to_re_delay':       {'r':( 8,11),'d':0x2,'c':'use for fixed delay, when reg_phy_use_fixed_re==1'}, #0x8

                  'reg_phy_wr_cmd_to_data':           {'r':( 4, 7),'d':0,'c':'Not used in DFI PHY'}, 

                  'reg_phy_rd_cmd_to_data':           {'r':( 0, 3),'d':0,'c':'Not used in DFI PHY'}}}, 

    'mode_sts_reg':            {'OFFS': 0x054,'DFLT':0x00000000,'RW':'R','FIELDS':{

    'mode_sts_reg':            {'OFFS': 0x054,'DFLT':0x00000000,'RW':'R','COMMENTS':'DDR Controller status','FIELDS':{

                  'ddrc_reg_dbg_hpr_q_depth':         {'r':(16,20),'d':0,'m':'R','c':'number in high priority read CAM'},   

                  'ddrc_reg_dbg_lpr_q_depth':         {'r':(10,15),'d':0,'m':'R','c':'number in low priority read CAM'},  

                  'ddrc_reg_dbg_wr_q_depth':          {'r':( 4, 9),'d':0,'m':'R','c':'number in write CAM '},

ezynq_feature_config.py

+3 −0
Original line number Diff line number Diff line
@@ -287,6 +287,9 @@ class EzynqFeatures: 
            else:        

                par_type={'H':'Integer','I':'Integer','F':'Float','B':'Boolean','T':'Text'}[feature['TYPE']]



#            if name=='BAUD_RATE':

#                print value



            html_file.write('<tr><th>'+feature['CONF_NAME']+'</th><td>'+str(value)+'</td><td>'+par_type+

                            '</td><td>'+('-','Y')[feature['MANDATORY']]+'</td><td>'+origin+'</td><td>'+str(feature['DEFAULT'])+'</td><td>'+feature['DESCRIPTION']+'</td></tr>\n')

        html_file.write('</table>\n')