Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
E
ezynq
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Wiki
Wiki
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Elphel
ezynq
Repository
01e77ff59d35dac2cf6df13be6acada5df73e61a
Switch branch/tag
ezynq
ezynq_ddr.py
Find file
Blame
History
Permalink
Working on UART support for dumping registers before DDR initialization
· 01e77ff5
Andrey Filippov
authored
Sep 20, 2013
01e77ff5
ezynq_ddr.py
114 KB
Edit
Web IDE
Replace ezynq_ddr.py
×
Attach a file by drag & drop or
click to upload
Commit message
Replace ezynq_ddr.py
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
