Commit 9685f884 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
Browse files

SSD mux script calling for Eyesis4Pi

parent 20229ca9

src/init_elphel393.py

+25 −12
Original line number Original line Diff line number Diff line
@@ -41,7 +41,7 @@ import os 




#params

#params

SENSOR_TYPE = 5

SENSOR_TYPE = 5

IPADDR = "192.168.0.9"

IPADDR = "192.168.0.8"

NETMASK = "255.255.255.0"

NETMASK = "255.255.255.0"

IMGSRV_PORT = 2323

IMGSRV_PORT = 2323

CAMOGM_PORT = 3456

CAMOGM_PORT = 3456
@@ -133,22 +133,35 @@ def init_imgsrv(port): 
def init_autoexp_daemon(index):

def init_autoexp_daemon(index):

    shout("autoexposure -p "+index+" -c 0 -b 0 -d 1 &")

    shout("autoexposure -p "+index+" -c 0 -b 0 -d 1 &")





def init_sata(sata_en,pydir):

def init_sata(sata_en):

    if os.path.isfile("/sys/devices/soc0/elphel393-pwr@0/detected_10389"):

    if os.path.isfile("/sys/devices/soc0/elphel393-pwr@0/detected_10389"):

        if (sata_en==1):

        if (sata_en==1):

            if not get_fpga():

            if not get_fpga():

                log_msg ("Waiting for the FPGA to be programmed to start SATA", 4)

                log_msg ("Waiting for the FPGA to be programmed to start SATA", 4)

                if not fpga_OK(TIMEOUT):

                if not fpga_OK(TIMEOUT):

                    print()

                    log_msg ("Timeout while waiting for the FPGA to be programmed", 2)

                    log_msg ("Timeout while waiting for the FPGA to be programmed", 2)

                    return

                    return

                else:

                else:

                    log_msg ("Done waiting for the FPGA", 4)

                    log_msg ("Done waiting for the FPGA", 4)

            shout(pydir+"/x393sata.py")  # Should be after modprobe? Wait for the FPGA should be before it

                    

            # the default connection is zynq <-> internal ssd 

            # default init will connect to internal SSD

            shout(pydir+"/x393sata_control.py set_zynq_ssd")

            shout(PYDIR+"/x393sata.py")  # Should be after modprobe? Wait for the FPGA should be before it

            # uncomment the line below for zynq <-> external ssd connection at boot

            

            # shout(pydir+"/x393sata_control.py set_zynq_esata")

            # for Eyesis4Pi (temporary fix)

            if switch['eyesis']!=0:

              

              log_msg ("Setting VSC3304 for Eyesis4Pi (driver will be loaded)", 4)

              log_msg ("  Details : /var/log/x393sata_eyesis4pi.log")

              log_msg ("  State   : /var/state/ssd")

              

              # Option 1: use internal SSDs: zynq <-> internal ssd

              # uncomment for use

              #shout(PYDIR+"/x393sata_eyesis4pi_control.py set_zynq_ssd")

              

              # Option 2: use external SSDs: zynq <-> external ssd

              # uncomment for use

              shout(PYDIR+"/x393sata_eyesis4pi_control.py set_zynq_esata")

            else:

              shout("modprobe ahci_elphel &")

              shout("modprobe ahci_elphel &")

              shout("sleep 2")

              shout("sleep 2")

              shout("echo 1 > /sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module")

              shout("echo 1 > /sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module")
@@ -272,7 +285,7 @@ if switch ['autocampars'] == 1: 
#6

#6

if switch['sata']==1:

if switch['sata']==1:

    log_msg("init SATA")

    log_msg("init SATA")

    init_sata(SATA_EN,PYDIR)

    init_sata(SATA_EN)

else:

else:

    log_msg("skip SATA")

    log_msg("skip SATA")