fwrite($confFile,createDefaultConfig($GLOBALS['version'],$port,$multisensor,$eyesis_mode));// use multisensor defaults if 10359 +sensors present
fclose($confFile);
log_msg("autocampars.php created a new configuration file $configPath from defaults.".($multisensor?(($eyesis_mode>0)?(' Used Eyesis mode, camera '.$eyesis_mode):' Used multisensor mode.'):''));
log_msg("port $port: autocampars.php created a new configuration file $configPath from defaults.".($multisensor?"This port is multiplexed":"").($GLOBALS['camera_state_arr']['is_eyesis']?(' Used Eyesis mode, camera '.$GLOBALS['camera_state_arr']['mode']?:' Used multisensor mode.'):''));\
<ol>This may (or may not) cause errors. You have several options:
<li> Follow <a href="?new&sensor_port={$port}">this link </a> and create a new config file </li>
<li> Follow <a href="?ignore-revision&sensor_port={$port}">this other link </a> to ignore the warning and write a new revision number to the config file</li>
...
...
@@ -1940,11 +2271,36 @@ function saveRotateConfig($sensor_port, $numBackups) {
<FOCUS_HEIGHT>"Focus WOI height (3 LSB will be zeroed as it should be multiple of 8x8 block height)"</FOCUS_HEIGHT>
<FOCUS_TOTWIDTH>"Total width of the image frame in pixels (readonly)"</FOCUS_TOTWIDTH>
<FOCUS_FILTER>"Select 8x8 filter used for the focus calculation (same order as quantization coefficients), 0..14"</FOCUS_FILTER>
<TRIG_CONDITION>"FPGA trigger sequencer trigger condition, 0 - internal, else dibits ((use<<1) | level) for each GPIO[11:0] pin). Example:0x200000 - input from external connector (J15 - http://wiki.elphel.com/index.php?title=10369#J15_-_SYNC_.28external.29 ), 0x20000 - input from internal (J13/J14 - http://wiki.elphel.com/index.php?title=10369#J13_-_SYNC_.28internal.2C_slave.29 )"</TRIG_CONDITION>
<TRIG_CONDITION>"FPGA trigger sequencer trigger condition, 0 - internal, else dibits: 00 - do not use, 01 - keep, 10 - active low, 11 - active high for each GPIO[9:0] pin). 10389 board inverts signals, so 0x80000 - input from external connector, 0x08000 - input from internal flex cable (as in Eyesis). "</TRIG_CONDITION>
<TRIG_DELAY>"FPGA trigger sequencer trigger delay, 32 bits in pixel clocks"</TRIG_DELAY>
<TRIG_OUT>"FPGA trigger sequencer trigger output to GPIO, dibits ((use << 1) | level_when_active). Bit 24 - test mode, when GPIO[11:10] are controlled by other internal signals. Example: 0x800000 - output to external (J15 - http://wiki.elphel.com/index.php?title=10369#J15_-_SYNC_.28external.29 ) connector, 0x80000 - to internal (J12 - http://wiki.elphel.com/index.php?title=10369#J12_-_SYNC_.28internal.2C_master.29 )"</TRIG_OUT>
<TRIG_OUT>"FPGA trigger sequencer trigger output to GPIO, dibits: 00 - do not use, 01 - keep, 10 - active low GPIO output, 11 - active high GPIO output. 10389 board inverts signals, so 0x02000 - output to external connector (active high), 0x20000 - output to internal flex connector"</TRIG_OUT>
<TRIG_PERIOD>"FPGA trigger sequencer output sync period (32 bits, in pixel clocks). 0- stop. 1 - single, >=256 repetitive with specified period"</TRIG_PERIOD>
<TRIG_BITLENGTH>"Bit length minus 1 (in pixel clock cycles) when transmitting/receiving timestamps, without timestamps the output pulse width is 8*(TRIG_BITLENGTH+1). Legal values 2..255."</TRIG_BITLENGTH>
<EXTERN_TIMESTAMP>"When 1 camera will use external timestamp (received over inter-camera synchronization cable) if it is available (no action when external syncronization is not connected), when 0 - local timestamp will be used"</EXTERN_TIMESTAMP>
