Commits · 7de9f2a38b6d9b9aa693562d6e32e7f6b8723c06 · Elphel / x393_sata

13 Mar, 2016 1 commit
- eliminating use of PLL with GTX · cb2fc48f
  Andrey Filippov authored Mar 13, 2016
  
  cb2fc48f
12 Mar, 2016 1 commit
- modified py393sata/ahci_fsm_sequence.py, rebuilt · 36c295d8
  Andrey Filippov authored Mar 12, 2016
  
  36c295d8
09 Mar, 2016 1 commit
- Added compact input primitives logging and FPGA-based profiling of the host/device communication · 29d789db
  Andrey Filippov authored Mar 09, 2016
  
  29d789db
07 Mar, 2016 1 commit
- Fixed link FSM error mishandling sender hold · 271e974e
  Andrey Filippov authored Mar 07, 2016
  
  271e974e
12 Feb, 2016 1 commit
- more debugging · 0e68732d
  Andrey Filippov authored Feb 12, 2016
  
  0e68732d
11 Feb, 2016 1 commit
- more testing with DRP · 507b1bd3
  Andrey Filippov authored Feb 11, 2016
  
  507b1bd3
06 Feb, 2016 1 commit
- got identify PIO data from the SSD · 50ca592a
  Andrey Filippov authored Feb 06, 2016
  
  50ca592a
21 Jan, 2016 1 commit
- Finished initial code, starting verification · ba05fb7c
  Andrey Filippov authored Jan 21, 2016
  
  ba05fb7c
29 Dec, 2015 1 commit
- Updated with vdt, adding comments/debug features, implemented required support for CONTp primitive · 6efdc1f7
  Andrey Filippov authored Dec 29, 2015
  
  6efdc1f7
09 Sep, 2015 1 commit
- Few more changes to make the project synth in vdt enviroment · e4816b14
  Alexey Grebenkin authored Sep 09, 2015
  
  e4816b14