fixed h2d (disk write), added cache control to Python script (fd942706) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Diff line number	Diff line
		@@ -52,87 +52,87 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160217100336765.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160217173227982.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160217100336765.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160217173227982.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160217100458164.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160217173341424.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160217100336765.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160217173227982.log</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-phys.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160217100458164.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160217173341424.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-power.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160217100458164.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160217173341424.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160217100458164.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160217173341424.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-place.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160217100458164.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160217173341424.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-route.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160217100458164.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160217173341424.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160217100336765.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160217173227982.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

ahci/ahci_dma_rd_fifo.v

+44 −14

Original line number	Diff line number	Diff line
		@@ -66,7 +66,9 @@ module ahci_dma_rd_fifo#(
		);
		localparam ADDRESS_NUM = (1<<ADDRESS_BITS); // 8 for ADDRESS_BITS==3
		reg [ADDRESS_BITS : 0] waddr; // 1 extra bit
		reg [ADDRESS_BITS+1:0] raddr; // 1 extra bit
		// reg [ADDRESS_BITS+1:0] raddr; // 1 extra bit
		reg [ADDRESS_BITS+1:0] raddr_r; // 1 extra bit
		wire [ADDRESS_BITS+1:0] raddr_w; // 1 extra bit
		reg [63:16] din_prev; // only 48 bits are needed
		reg [WCNT_BITS-3:0] qwcntr;
		reg busy;
		@@ -92,8 +94,10 @@ module ahci_dma_rd_fifo#(
		wire [63:0] fifo_di= woffs_r[1]?(woffs_r[0] ? {din[47:0],din_prev[63:48]} : {din[31:0],din_prev[63:32]}):
		(woffs_r[0] ? {din[15:0],din_prev[63:16]} : din[63:0]);
		wire [3:0] fifo_di_vld;
		wire [63:0] fifo_do = fifo_ram [raddr[ADDRESS_BITS:1]];
		wire [3:0] fifo_do_vld = vld_ram [raddr[ADDRESS_BITS:1]];
		// wire [63:0] fifo_do = fifo_ram [raddr[ADDRESS_BITS:1]];
		// wire [3:0] fifo_do_vld = vld_ram [raddr[ADDRESS_BITS:1]];
		reg [63:0] fifo_do_r;
		reg [3:0] fifo_do_vld_r;
		reg din_av_safe_r;
		reg en_fifo_wr;
		reg [3:0] last_mask;
		@@ -109,9 +113,19 @@ module ahci_dma_rd_fifo#(


		wire [2:0] debug_waddr = waddr[2:0];
		wire [2:0] debug_raddr = raddr[3:1];
		wire [2:0] debug_raddr = raddr_r[3:1];
		// just for gtkwave - same names
		wire [ADDRESS_BITS+1:0] raddr = raddr_r;
		wire [63:0] fifo_do = fifo_do_r;
		wire [3:0] fifo_do_vld = fifo_do_vld_r;


		// assign fifo_dav2_w = fifo_full2[raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];
		/// assign fifo_dav2_w = fifo_full2[raddr_r[ADDRESS_BITS:1]] ^ raddr_r[ADDRESS_BITS+1];
		assign fifo_dav2_w = fifo_full2[raddr_w[ADDRESS_BITS:1]] ^ raddr_w[ADDRESS_BITS+1];



		assign fifo_dav2_w = fifo_full2[raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];
		assign last_fifo_wr = !busy \|\| ((qwcntr == 0) && ((woffs == 0) \|\| end_offs[2])); // ((qwcntr != 0) \|\| ((woffs != 0) && last_prd));


		@@ -152,26 +166,40 @@ module ahci_dma_rd_fifo#(
		if (mrst_hclk) din_av_safe_r <= 0;
		else din_av_safe_r <= din_av && (din_av_many \|\| !din_re);

		if (start) last_mask <= {&wcnt, wcnt[1], \|wcnt, 1'b1};
		if (start) last_mask <= {&wcnt[1:0], wcnt[1], \|wcnt[1:0], 1'b1};

		if (mrst_hclk \|\| done_flush) flushing_hclk <= 0;
		else if (fifo_wr && last_prd && (((qwcntr == 0) && ((woffs == 0) \|\| !last_prd)) \|\| !busy)) flushing_hclk <= 1;

		end

		assign raddr_w = mrst ? 0 : (raddr_r + fifo_rd);

		always @ (posedge mclk) begin

		fifo_rd_r <= {fifo_rd_r[0],fifo_rd};
		if (mrst) raddr <= 0;
		else if (fifo_rd) raddr <= raddr + 1;
		// if (mrst) raddr <= 0;
		// else if (fifo_rd) raddr <= raddr + 1;

		raddr_r <= raddr_w;

		if (mrst) fifo_nempty <= {{(ADDRESS_NUM>>1){1'b0}},{(ADDRESS_NUM>>1){1'b1}}};// 8'b00001111
		else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0], ~raddr[ADDRESS_BITS+1] ^ raddr[ADDRESS_BITS]};
		// else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0], ~raddr[ADDRESS_BITS+1] ^ raddr[ADDRESS_BITS]};
		else if (fifo_rd && raddr_r[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0], ~raddr_r[ADDRESS_BITS+1] ^ raddr_r[ADDRESS_BITS]};

		// fifo_dav <= fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];
		/// fifo_dav <= fifo_full [raddr_r[ADDRESS_BITS:1]] ^ raddr_r[ADDRESS_BITS+1];
		fifo_dav <= fifo_full [raddr_w[ADDRESS_BITS:1]] ^ raddr_w[ADDRESS_BITS+1];


		fifo_dav <= fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];
		fifo_dav2 <= fifo_dav2_w; // fifo_full2[raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1];

		if (mrst) flushing_mclk <= 0;
		else flushing_mclk <= flushing_hclk;

		fifo_do_r <= fifo_ram [raddr_w[ADDRESS_BITS:1]];
		fifo_do_vld_r <= vld_ram [raddr_w[ADDRESS_BITS:1]];

		end

		ahci_dma_rd_stuff ahci_dma_rd_stuff_i (
		@@ -181,8 +209,10 @@ module ahci_dma_rd_fifo#(
		.din_avm_w(fifo_dav2_w), // input
		.din_avm (fifo_dav2), // input
		.flushing (flushing_mclk), // input
		.din (raddr[0]?fifo_do[63:32]: fifo_do[31:0]), // input[31:0]
		.dm (raddr[0]?fifo_do_vld[3:2]:fifo_do_vld[1:0]), // input[1:0]
		// .din (raddr[0]?fifo_do[63:32]: fifo_do[31:0]), // input[31:0]
		// .dm (raddr[0]?fifo_do_vld[3:2]:fifo_do_vld[1:0]), // input[1:0]
		.din (raddr_r[0]?fifo_do_r[63:32]: fifo_do_r[31:0]), // input[31:0]
		.dm (raddr_r[0]?fifo_do_vld_r[3:2]:fifo_do_vld_r[1:0]), // input[1:0]
		.din_re (fifo_rd), // output
		.flushed (done_flush_mclk), // output reg: flush (end of last PRD is finished - data left module)
		.dout (dout), // output[31:0] reg
		@@ -205,8 +235,8 @@ module ahci_dma_rd_fifo#(
		assign debug_dma_h2d = {
		14'b0,
		fifo_rd,
		raddr[4:0],
		fifo_do_vld[3:0],
		raddr_r[4:0],
		fifo_do_vld_r[3:0],

		fifo_dav,
		fifo_dav2_w,

ahci/ahci_top.v

+29 −2

Original line number	Diff line number	Diff line
		@@ -1107,7 +1107,15 @@ wire [9:0] xmit_dbg_01;
		debug_dma_h2d[0], // last_DW,

		dma_dout[27:16],
		debug_dma_h2d[19:4]
		debug_dma_h2d[19:18], // 2'b0
		debug_dma_h2d[17], // fifo_rd
		debug_dma_h2d[16:12], // raddr[4:0]
		debug_dma_h2d[11:8], //fifo_do_vld[3:0]

		debug_dma_h2d[7], // fifo_dav
		debug_dma_h2d[6], // fifo_dav2_w
		debug_dma_h2d[5], // fifo_dav2
		debug_dma_h2d[4] // flushing_mclk
		};

		// dma_dout[
		@@ -1125,7 +1133,26 @@ wire [9:0] xmit_dbg_01;


		end
		/*debug_dma_h2d
		/*
		debug_dma_h2d[3], // done_flush_mclk,
		debug_dma_h2d[2], // dout_vld,
		debug_dma_h2d[1], // dout_re,
		debug_dma_h2d[0], // last_DW,

		dma_dout[27:16],
		debug_dma_h2d[19:18], // 2'b0
		debug_dma_h2d[17], // fifo_rd
		debug_dma_h2d[16:12], // raddr[4:0]
		debug_dma_h2d[11:8], //fifo_do_vld[3:0]

		debug_dma_h2d[7], // fifo_dav
		debug_dma_h2d[6], // fifo_dav2_w
		debug_dma_h2d[5], // fifo_dav2
		debug_dma_h2d[4] // flushing_mclk



		debug_dma_h2d
		assign debug_dma_h2d = {
		14'b0,
		17 fifo_rd,

py393sata/x393sata.py

+25 −2

Original line number	Diff line number	Diff line
		@@ -976,6 +976,27 @@ class x393sata(object):
		prev_dword = dword
		print()

		def cache_mode(self, write_mode=None, read_mode=None):
		"""
		Change AXI cache mode for SAXIHP3.
		@param write_mode - 0..15 - AXI cache mode for writing to the system memory (none - keep current)
		@param read_mode - 0..15 - AXI cache mode for reading from the system memory (none - keep current)
		bit 0 (B) for writes - bufferable
		bit 1 (C) cacheable
		bit 2 (RA) read allocate, should not be 1 if C==0
		bit 3 (WA) write allocate, should not be 1 if C==0
		"""
		mode =self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__AFI_CACHE'))
		if (write_mode is None) and (read_mode is None):
		print("Current AXI HP cache mode is set to: write = 0x%x, read = 0x%x"%((mode >> 4) & 0xf, (mode >> 0) & 0xf))
		else:
		if not write_mode is None:
		mode = ((mode ^ ((write_mode & 0xf) << 4)) & (0xf << 4)) ^ mode
		if not read_mode is None:
		mode = ((mode ^ ((reade_mode & 0xf) << 0)) & (0xf << 0)) ^ mode
		self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__AFI_CACHE'), mode)

		return {'write':(mode >> 4) & 0xf, 'read':(mode >> 0) & 0xf}

		"""

		@@ -1071,13 +1092,14 @@ for block in range (1,1024):

		for i in range(128):
		mem.write_mem(x393sata.DATAOUT_ADDRESS + 4i,2i + ((254-2i)<<8) + ((2i+1)<<16) + ((255-2*i) << 24))

		_=mem.mem_dump(x393sata.DATAOUT_ADDRESS,128,4)
		_=mem.mem_dump(x393sata.DATAOUT_ADDRESS,256,2)

		sata.dd_write_dma(9,1)
		_=mem.mem_dump (0x80000ff0, 4,4)

		_=mem.mem_dump (0x80001000, 0x200,4)
		_=mem.mem_dump (0x80001000, 0x400,4)



		@@ -1085,6 +1107,7 @@ sata.arm_logger()
		sata.setup_pio_read_identify_command()

		sata.datascope1()
		sata.dd_read_dma(1, 1)

tb/tb_ahci.tf

+40 −1

Original line number	Diff line number	Diff line
		@@ -1040,6 +1040,43 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
		end
		endtask

		task setup_dma_write_identify_command_simple; // Write DMA, use data received during read identify
		input integer lba;
		input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
		integer i;

		begin
		// clear system memory for command
		for (i = 0; i < 64; i = i+1) sysmem[(COMMAND_TABLE >> 2) + i] = 0;
		// fill ATA command
		sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR \| // FIS type - H2D register (0x27)
		('h80 << 8) \| // set C = 1
		(ATA_WDMA << 16) \| // Command = 0xCA
		( 0 << 24); // features = 0 ?
		sysmem[(COMMAND_TABLE >> 2) + 1] = lba & 'hffffff; // 24 LSBs of LBA (48-bit require different ATA command)
		sysmem[(COMMAND_TABLE >> 2) + 3] = 1; // 1 logical sector (0 means 256)
		// All other DWORDs are 0 for this command
		// Set PRDT (four items)
		// PRDT #1
		sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF; // not shifted
		sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) \| (512 - 1); // 512 bytes in this PRDT

		// Setup command header
		maxigp1_writep ((CLB_OFFS32 + 0) << 2, (5 << 0) \| // 'CFL' - number of DWORDs in thes CFIS
		(0 << 5) \| // 'A' Not ATAPI
		(1 << 6) \| // 'W' Is write to device
		(1 << 7) \| // 'P' Prefetchable = 1
		(0 << 8) \| // 'R' Not a Reset
		(0 << 9) \| // 'B' Not a BIST
		// (0 << 10) \| // 'C' Do not clear BSY/CI after transmitting this command
		(1 << 10) \| // 'C' Do clear BSY/CI after transmitting this command
		(1 << 16)); // 'PRDTL' - number of PRDT entries (1)
		maxigp1_writep ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
		// Set Command Issued
		maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
		// relax and enjoy
		end
		endtask


		reg [15:0] drp_read_data;
		@@ -1227,7 +1264,9 @@ initial begin //Host
		maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one)
		wait (~IRQ);

		setup_dma_write_identify_command_multi4(1,'h123456, 27,71,83); // LBA = 'h123456
		// setup_dma_write_identify_command_multi4(1,'h123456, 27,71,83); // LBA = 'h123456 seems wrong order
		setup_dma_write_identify_command_multi4('h123456, 1, 27,71,83); // LBA = 'h123456
		/// setup_dma_write_identify_command_simple('h123456, 1);
		TESTBENCH_TITLE = "Set DMA Write command for device";
		$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);

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