This version tested with AHCI controller

.project

@@ -52,87 +52,87 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160229184939748.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160304125744608.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160229184939748.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160304125744608.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160229185157261.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160304130042850.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160229184939748.log</location>
+			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160304125744608.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160229185157261.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160304130042850.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt-power.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160229185157261.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160304130042850.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-opt.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160229185157261.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160304130042850.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160229185157261.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160304130042850.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160229185157261.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160304130042850.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393_sata-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160229184939748.dcp</location>
+			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160304125744608.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

ahci/ahci_fis_receive.v

@@ -342,7 +342,7 @@ localparam DATA_TYPE_ERR =      3;
         if (reg_we_w)                         reg_data <=    hba_data_in;
         else if (update_err_sts_r)            reg_data <=    {16'b0,tf_err_sts};
         else if (update_sig_r)                reg_data <=    sig_r;
-        else if (update_prdbc_r)              reg_data <=    {xfer_cntr_r[31:2],2'b0};
+        else if (update_prdbc_r)              reg_data <=    {prdbc_r[31:2],2'b0}; // xfer_cntr_r[31:2],2'b0};
 
         if (store_sig[1])                     sig_r[31:8] <= hba_data_in[23:0];
         if (store_sig[3])                     sig_r[ 7:0] <= hba_data_in[ 7:0];

ahci/ahci_top.v

@@ -1295,9 +1295,9 @@ debug_dma_h2d
                                                                                                        debug_in_link[23],
                                                                                                        datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
     always @(posedge mclk) begin
-        if    (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START; // start from command FIS
+        if    (fsnd_cfis_xmit)                          datascope_waddr_r <= DATASCOPE_CFIS_START; // start from command FIS
 ///        if    (mrst) datascope_waddr_r <= DATASCOPE_CFIS_START;
-        else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
+        else if (datascope_we && !(&datascope_waddr_r)) datascope_waddr_r <= datascope_waddr_r + 1;
     end
 
 `else    

device/sata_device.v

@@ -850,6 +850,19 @@ task send_identify_data; // @SuppressThisWarning VEditor - Used in testbench
     end
 endtask
 
+task send_incrementing_data; // @SuppressThisWarning VEditor - Used in testbench
+    input integer id;
+    input integer len;
+    output integer status;
+    integer i;
+    begin
+        transmit_data[0] = FIS_DATA;
+        for (i=0;i<len;i=i+1) begin
+            transmit_data[i+1] = i;
+        end
+        linkTransmitFIS(id, 129, 0, status);        
+    end
+endtask
 
 
 

generated/action_decoder.v

 /*******************************************************************************
  * Module: action_decoder
- * Date:2016-02-29  
+ * Date:2016-03-03  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Decode sequencer code to 1-hot actions
  *******************************************************************************/

generated/condition_mux.v

 /*******************************************************************************
  * Module: condition_mux
- * Date:2016-02-29  
+ * Date:2016-03-03  
  * Author: auto-generated file, see ahci_fsm_sequence.py
  * Description: Select condition
  *******************************************************************************/

py393sata/x393_vsc3304.py

@@ -57,6 +57,14 @@ class x393_vsc3304(object):
             "SSD_B":          "F",
             "ZYNQ_A":         "G",
             "ZYNQ_B":         "H"},
+        "10389S": { #testing with the wrong adapter
+            "INVERTED_PORTS": ("C","E","G","H"),
+            "ESATA_A":        "C",
+            "ESATA_B":        "A",
+            "SSD_A":          "E",
+            "SSD_B":          "F",
+            "ZYNQ_A":         "G",
+            "ZYNQ_B":         "H"},
      }
     PORT_NUM = {"A":{"OUT": 8,"IN":12}, # I/O port numbers for each port name
                 "B":{"OUT": 9,"IN":13},
@@ -77,6 +85,9 @@ class x393_vsc3304(object):
 
         "ZYNQ<->ESATA":[{"FROM": "ZYNQ_A",  "TO": "ESATA_A" },
                         {"FROM": "ESATA_B", "TO": "ZYNQ_B"}],
+        #Temporarily, testing with wrong adapter  (swapped ESATA_A and ESATA_B)                 
+        "ZYNQ<->SSATA":[{"FROM": "ZYNQ_A",  "TO": "ESATA_B" },
+                        {"FROM": "ESATA_A", "TO": "ZYNQ_B"}],
                            
         "DEBUG_SSD":   [{"FROM": "ZYNQ_A",  "TO": "SSD_A" },
                         {"FROM": "SSD_B",   "TO": "ZYNQ_B"},
@@ -188,6 +199,9 @@ class x393_vsc3304(object):
 
     def connect_zynq_esata(self):
         self.connect("ZYNQ<->ESATA")
+
+    def connect_zynq_ssata(self):
+        self.connect("ZYNQ<->SSATA")
         
     def connect_debug(self):
         self.connect("DEBUG_SSD")

tb/tb_ahci.tf

@@ -817,6 +817,7 @@ localparam ATA_WBUF_DMA = 'heb; // Write 512 bytes to device buffer in DMA mode
 localparam ATA_RDMA =     'hc8; // Read from device in DMA mode                   @SuppressThisWarning VEditor - not yet used
 localparam ATA_RBUF_PIO = 'he4; // Read  512 bytes from device buffer in PIO mode @SuppressThisWarning VEditor - not yet used
 localparam ATA_RBUF_DMA = 'he9; // Read  512 bytes from device buffer in DMA mode @SuppressThisWarning VEditor - not yet used
+localparam ATA_RDMA_EXT = 'h25; // Read DMA devices that support 48-bit Addressing
 
     reg  [31:0] sysmem[0:4095]; 
 
@@ -996,6 +997,60 @@ localparam ATA_RBUF_DMA = 'he9; // Read  512 bytes from device buffer in DMA mod
         end
     endtask
     
+    task setup_dma_read_ext_command_multi4;
+        input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
+        input integer nw1; // first segment lengtth (in words)
+        input integer nw2; // second segment lengtth (in words)
+        input integer nw3; // third segment lengtth (in words)
+        
+        integer nw4;
+        integer i;
+        
+        begin
+            nw4 = 256 - nw1 - nw2 - nw3; // total 512 bytes, 256 words
+            // clear system memory for command
+            for (i = 0; i < 64; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;
+            // fill ATA command 
+            sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR |         // FIS type - H2D register (0x27)
+                                               ('h80 << 8) |      // set C = 1
+                                               (ATA_RDMA_EXT << 16) | // Command = 0x25 (READ_DMA_EXT)
+                                              ( 0 << 24);        // features = 0 ?
+            // All other 4 DWORDs are 0 for this command
+            // Set PRDT (four items)
+            // PRDT #1
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  0] = SYS_MEM_START + IDENTIFY_BUF; // not shifted
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  3] = (prd_int[0] << 31) | (2 * nw1 - 1); // 2 * nw1 bytes
+            // PRDT #2
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  4] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1);
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  7] = (prd_int[0] << 31) | (2 * nw2 - 1); // 2 * nw2 bytes
+            // PRDT #3
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  8] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1) + (2 * nw2);
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 11] = (prd_int[0] << 31) | (2 * nw3 - 1); // 2 * nw3 bytes
+            // PRDT #4
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 12] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1) + (2 * nw2) + (2 * nw3);
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 15] = (prd_int[0] << 31) | (2 * nw4 - 1); // 2 * nw4 bytes
+            
+            // Setup command header
+            maxigp1_writep       ((CLB_OFFS32 + 0) << 2, (5 <<  0) | // 'CFL' - number of DWORDs in the CFIS
+                                                         (0 <<  5) | // 'A' Not ATAPI
+                                                         (0 <<  6) | // 'W' Not write to device
+//                                                         (1 <<  7) | // 'P' Prefetchable = 1
+                                                         (0 <<  7) | // 'P' Prefetchable = 1
+                                                         (0 <<  8) | // 'R' Not a Reset
+                                                         (0 <<  9) | // 'B' Not a BIST
+                                                         (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command
+//                                                         (1 << 10) | // 'C' Do clear BSY/CI after transmitting this command
+                                                         (4 << 16)); // 'PRDTL' - number of PRDT entries (4)
+///            maxigp1_writep       ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address
+            maxigp1_writep       ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE)); // 'CTBA' - Command table base address
+            // Set Command Issued
+            maxigp1_writep       (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)
+            // relax and enjoy
+        end
+    endtask
+    
+    
+    
     task setup_dma_write_identify_command_multi4; // Write DMA, use data received during read identify
         input integer lba;
         input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
@@ -1205,9 +1260,13 @@ initial begin //Host
     maxigp1_print        (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");
     
 //  setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
-  setup_pio_read_identify_command_simple(2560,1); // intentionally too long
+
+////  setup_pio_read_identify_command_simple(2560,1); // intentionally too long
 ///  setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0
-/// setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0
+
+/// setup_pio_read_identify_command_multi4(0,27,71,83); // No prdt interrupts
+    setup_dma_read_ext_command_multi4(0,64,64,64);     // No prdt interrupts, 4 64-word chunks
+    
 /// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0
 ///    setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used
     maxigp1_print        (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
@@ -1323,6 +1382,13 @@ initial begin //Host
 //HBA_PORT__PxIE__DHRE__MASK = 'h1;
 end
 
+function func_is_dev_read_dma_ext;
+    input [31:0] dw;
+    begin
+        func_is_dev_read_dma_ext = ((dw & 'hff) == FIS_H2DR ) && (((dw >> 16) & 'hff) == ATA_RDMA_EXT);
+    end
+endfunction
+
 function func_is_dev_identify;
     input [31:0] dw;
     begin
@@ -1390,13 +1456,32 @@ initial begin //Device
 
             dev.send_dma_activate (69,      // input integer id;
                                    status); // output integer status;
+        end else if (func_is_dev_read_dma_ext(dev.receive_data[0])) begin
+            dev.send_incrementing_data(70,      // input integer id;
+                                   128, // number of dwords to send, later decode count field
+                                   status); // output integer status;
+            DEVICE_TITLE =                "Device sent Data FIS (READ DMA EXT)";
+            $display("[Dev-TB]:            %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
+            
+            // Send multiple FISes if needed, when done:
+            dev.send_D2HR(70,
+               1, // irq,
+               8'h0,                                // status
+               0,                                   // error
+               0,                                   // device
+               0,                                   // lba_low
+               0,                                   // lba_high
+               0,                                   // count
+               status);                             // output: result status
+            DEVICE_TITLE =                "Device sent D2H FIS (DMA D2H over)";
+            $display("[Dev-TB]:            %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
 
         end else if (func_is_h2d_data(dev.receive_data[0])) begin
             DEVICE_TITLE = "Got H2D data";
             $display("[Dev-TB]:       %s @%t", DEVICE_TITLE, $time);
             $display("[Dev-TB]:       %hh payload DWORDs got (%d bytes) @%t", dev.received_size, dev.received_size << 2, $time);
             // Assuming device got what it needed, otherwise send DMA Activate again
-            dev.send_D2HR(70,
+            dev.send_D2HR(71,
                1, // irq,
                8'h0,                                // status
                0,                                   // error

tb_ahci_01.sav

 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Tue Mar  1 01:47:21 2016
+[*] Fri Mar  4 19:49:47 2016
 [*]
-[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160229184025832.fst"
-[dumpfile_mtime] "Tue Mar  1 01:42:30 2016"
-[dumpfile_size] 15004446
+[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160304124651260.fst"
+[dumpfile_mtime] "Fri Mar  4 19:48:48 2016"
+[dumpfile_size] 13922108
 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
-[timestart] 47816000
+[timestart] 34498000
 [size] 1823 1180
 [pos] 0 42
-*-18.256386 48747934 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-19.415150 37229086 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb_ahci.
 [treeopen] tb_ahci.axi_read_addr.
+[treeopen] tb_ahci.dev.
 [treeopen] tb_ahci.dev.linkMonitorFIS.
 [treeopen] tb_ahci.dev.phy.
 [treeopen] tb_ahci.dev.phy.gtx_wrapper.
 [treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.
 [treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.
+[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.
+[treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.
 [treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.
 [treeopen] tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.ser.
 [treeopen] tb_ahci.dev.phy.oob_dev.
@@ -56,8 +59,8 @@
 [treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
 [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
 [treeopen] tb_ahci.simul_axi_read_i.
-[sst_width] 368
-[signals_width] 409
+[sst_width] 325
+[signals_width] 338
 [sst_expanded] 1
 [sst_vpaned_height] 573
 @820
@@ -1702,7 +1705,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
 -drp
 @1401200
 -axi_ahci_regs
-@c00200
+@800200
 -ahci_fsm
 @28
 tb_ahci.dut.sata_top.ahci_top_i.hba_arst
@@ -1837,6 +1840,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.sirq_PC
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.get_rfis
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_sig
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_prdbc
 @1000200
 -actions
 @c00200
@@ -1976,7 +1980,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
-@1401200
+@1000200
 -ahci_fsm
 @c00200
 -ahci_fis_receive
@@ -2533,16 +2537,38 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
 -
 @800200
 -debug_non_prefetchable
+@29
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.XFER0
+@28
+tb_ahci.dut.sata_top.ahci_top_i.dma_cmd_busy
+tb_ahci.dut.sata_top.ahci_top_i.dma_cmd_done
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_prds_done
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dwords_over
+@22
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.data_in_dwords_r[11:0]
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.prdbc_r[31:2]
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.get_data_fis
+tb_ahci.dut.sata_top.ahci_top_i.frcv_update_prdbc
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.update_prdbc
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.update_prdbc_r
+@22
+tb_ahci.dut.sata_top.ahci_top_i.xfer_cntr[31:2]
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.xfer_cntr_r[31:2]
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_data[31:0]
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr[9:0]
+@28
+tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_we
+@200
+-
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_pio
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts
 (1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions_w
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_bsy
-@29
 [color] 3
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.conditions_ce
-@28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_drq
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_sts[7:0]
@@ -2802,7 +2828,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_len[3:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_addr_data_w
-@800200
+@c00200
 -fifo_h2d
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.din[63:0]
@@ -3175,7 +3201,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.slow_down
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.last_DW
-@800200
+@c00200
 -debug
 @200
 -
@@ -3223,10 +3249,12 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.last_dw_sent
 @1001200
 -group_end
-@1000200
+@1401200
 -debug
+@1000200
 -h2d_stuff
 -mclk_domain
+@1401200
 -fifo_h2d
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_busy
@@ -4221,6 +4249,20 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.crc_bit[31:0]
 @1000200
 -crc
 @800200
+-dev_dbg
+@28
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.reset
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.full_wr
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.val_wr
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.dataiface.val_rd
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.des.need_reset
+@22
+tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.rx.des.bitcounter[31:0]
+@200
+-
+@1000200
+-dev_dbg
+@800200
 -dev_crc
 @22
 tb_ahci.dev.phy.ll_data_out[31:0]
@@ -5238,7 +5280,7 @@ tb_ahci.dut.sata_top.ahci_top_i.h2d_valid
 tb_ahci.dut.sata_top.ahci_top_i.data_out_dwords[11:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.datascope_clk
-@800022
+@c00022
 tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@@ -5273,7 +5315,7 @@ tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
 (29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
 (30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
 (31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
-@1001200
+@1401200
 -group_end
 @800022
 tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0]

wrapper/GTXE2_GPL.v

@@ -1282,7 +1282,7 @@ assign  val_wr  = ~full_wr & bitcounter == (width - 1);
 always @ (posedge inclk) begin
     if (reset) need_reset <= 0;
     else if (full_wr && !need_reset) begin
-        $display("FIFO in %m is full, that is not an appropriate behaviour - needs reset @%time", $time);
+        $display("1:FIFO in %m is full, that is not an appropriate behaviour - needs reset @%time", $time);
         bitcounter <= 'bx;
         need_reset <= 1'b1;
 //        $finish;
@@ -1811,6 +1811,7 @@ wire                    full_wr;
 wire                    val_wr;
 wire                    val_rd;
 wire                    almost_empty_rd;
+reg                     need_reset = 1;
 
 always @ (posedge usrclk)
     wordcounter  <= reset ? 32'h0 : realign & ~(div == 0) ? 32'd1 : wordcounter == (div - 1) ? 32'h0 : wordcounter + 1'b1;
@@ -1835,10 +1836,11 @@ assign  val_rd  = ~empty_rd & ~almost_empty_rd;
 assign  val_wr  = ~full_wr & wordcounter == (div - 1);
 
 always @ (posedge usrclk)
-    if (full_wr)
-    begin
-        $display("FIFO in %m is full, that is not an appropriate behaviour, needs reset");
+    if (reset) need_reset <= 0;
+    else   if (full_wr && !need_reset) begin
+        $display("2:FIFO in %m is full, that is not an appropriate behaviour, needs reset @%time", $time);
         wordcounter = 'bx;
+        need_reset <= 1;
 //        $finish;
     end