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x393_sata
Commit f64d20dd authored by Andrey Filippov's avatar Andrey Filippov
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more debugging

parent ca5c6e32
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Showing with 411 additions and 52 deletions
ahci/ahci_ctrl_stat.v
View file @ f64d20dd
......@@ -225,7 +225,9 @@ module ahci_ctrl_stat #(
reg sirq_changed;
reg pxcmd_changed;
reg ghc_is_changed;
wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
// wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
wire [5:0] regs_changed={pxci_changed, pxcmd_changed, serr_changed, ssts_changed, sirq_changed,ghc_is_changed };
// wire [5:0] update;
reg [5:1] updating;
wire [5:0] update_first = {6{update_all}} &
......
ahci/ahci_sata_layers.v
View file @ f64d20dd
......@@ -178,20 +178,20 @@ module ahci_sata_layers #(
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
assign phy_speed = phy_ready ? PHY_SPEED:0;
assign serr_DB = |ph2ll_err_out;
assign serr_DH = xmit_err;
assign serr_DB = phy_ready && (|ph2ll_err_out);
assign serr_DH = phy_ready && (xmit_err);
// not yet assigned errors
assign serr_DT = 0; // RWC: Transport state transition error
assign serr_DS = 0; // RWC: Link sequence error
assign serr_DC = 0; // RWC: CRC error in Link layer
assign serr_DB = 0; // RWC: 10B to 8B decode error
assign serr_DI = 0; // RWC: PHY Internal Error
assign serr_EP = 0; // RWC: Protocol Error - a violation of SATA protocol detected
assign serr_EC = 0; // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = 0; // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = 0; // RWC: Communication between the device and host was lost but re-established
assign serr_EI = 0; // RWC: Recovered Data integrity Error
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
......
ahci/ahci_top.v
View file @ f64d20dd
......@@ -202,8 +202,8 @@ module ahci_top#(
wire [ADDRESS_BITS-1:0] regs_raddr;
wire [31:0] regs_din_from_freceive;
wire [31:0] regs_dout;
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we}} & regs_waddr) |
({ADDRESS_BITS{regs_re[0]}} & regs_raddr) |
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) |
({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) |
// ({ADDRESS_BITS{regs_re_fsm[0] | regs_we_acs}} & regs_saddr);
({ADDRESS_BITS{regs_we_acs}} & regs_saddr);
......
ahci/axi_ahci_regs.v
View file @ f64d20dd
......@@ -151,7 +151,8 @@ module axi_ahci_regs#(
reg write_busy_r;
wire write_start_burst;
// wire nowrite; // delay write in read-modify-write register accesses
wire write_busy_w = write_busy_r || write_start_burst;
/// wire write_busy_w = write_busy_r || write_start_burst;
wire write_busy_w = write_busy_r || write_start_burst || bram_wen_r;
reg [31:0] bram_wdata_r;
reg [31:0] bram_rdata_r;
// reg bram_wen_d;
......@@ -186,9 +187,14 @@ module axi_ahci_regs#(
reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
reg bram_ren0_r;
wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // axibram_read does not mask bram_ren and bram_regen with dev_ready !
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
assign port_arst = port_rst_r; // port _reset by software
assign port_arst_any = port_arst_any_r;
......@@ -197,13 +203,15 @@ module axi_ahci_regs#(
always @(posedge aclk) begin
bram_ren0_r <= bram_ren_w[0];
if (arst) write_busy_r <= 0;
else if (write_start_burst) write_busy_r <= 1;
else if (!pre_bram_wen) write_busy_r <= 0;
if (bram_wen) bram_wdata_r <= bram_wdata;
if (bram_ren[1]) bram_rdata_r <= bram_rdata;
if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
......@@ -394,7 +402,9 @@ sata_phy_rst_out will be released after the sata clock is stable
) ahci_regs_i (
.clk_a (aclk), // input
.addr_a (bram_addr), // input[9:0]
.en_a (bram_ren[0] || write_busy_w), // input
/// .en_a (bram_ren[0] || write_busy_w), // input
/// .en_a (bram_ren[0] || bram_wen || bram_wen_r), // input
.en_a (bram_ren_w[0] || bram_wen || bram_wen_r), // input
.regen_a (1'b0), // input
// .we_a (write_busy_r && !nowrite), // input
.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]
......
tb/tb_ahci.tf
View file @ f64d20dd
......@@ -626,6 +626,17 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
end
endtask
task maxigp1_writep; // address in bytes, not words
input [31:0] address;
input [31:0] data;
begin
axi_write_single(address + MAXIGP1, data);
$display ("%x <- %x @ %t",address + MAXIGP1, data,$time);
end
endtask
task maxigp1_read;
input [31:0] address;
begin
......@@ -653,9 +664,15 @@ initial begin //Host
axi_set_rd_lag(0);
axi_set_b_lag(0);
maxigp1_print(PCI_Header__CAP__CAP__ADDR);
maxigp1_print(GHC__PI__PI__ADDR);
maxigp1_print(HBA_PORT__PxCMD__ICC__ADDR);
maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);
maxigp1_print (GHC__PI__PI__ADDR << 2);
maxigp1_print (HBA_PORT__PxCMD__ICC__ADDR << 2);
maxigp1_print (GHC__GHC__IE__ADDR << 2);
maxigp1_writep (GHC__GHC__IE__ADDR << 2, GHC__GHC__IE__MASK); // enable interrupts (global)
maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);
maxigp1_writep (HBA_PORT__PxIE__CPDE__ADDR << 2, ~0); // allow all interrupts
maxigp1_print (GHC__GHC__IE__ADDR << 2);
maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);
// $finish;
......
tb_ahci_01.sav
View file @ f64d20dd
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Jan 23 23:40:23 2016
[*] Sun Jan 24 07:52:42 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160123162627844.fst"
[dumpfile_mtime] "Sat Jan 23 23:27:24 2016"
[dumpfile_size] 6302723
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160124004810793.fst"
[dumpfile_mtime] "Sun Jan 24 07:49:05 2016"
[dumpfile_size] 6307339
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 15250600
[size] 1823 1180
[timestart] 646000
[size] 1823 1173
[pos] 1951 0
*-16.074623 15525400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-17.936193 1430000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.phy.
......@@ -22,11 +22,14 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[sst_width] 275
[signals_width] 249
[signals_width] 254
[sst_expanded] 1
[sst_vpaned_height] 625
@820
......@@ -46,6 +49,88 @@ tb_ahci.dut.RXN
-axi_ahci_regs
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.dev_ready
@800028
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
@29
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
@1001200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_rdata_r[31:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.pre_bram_wen
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen_r
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_waddr_r[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata_r[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_a
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
@1401200
-group_end
@800022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.data_in32_a[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
@1001200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_busy_w
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_rdata[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_di[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.regbit_type[63:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wmask[31:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_we
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_re[1:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_din[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_dout[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.high_sel
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_start_burst
@200
-
@c00200
-axibram_read
@22
......@@ -78,7 +163,7 @@ tb_ahci.rstb
-axibram_read
@1000200
-axi_ahci_regs
@800200
@c00200
-ahci_sata_layers
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.exrst
......@@ -110,15 +195,78 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen
-
@1000200
-fifo_d2h_control
@1401200
-ahci_sata_layers
@800200
-ahci_top
@22
tb_ahci.dut.sata_top.ahci_top_i.regs_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.regs_raddr[9:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.regs_addr[9:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.regs_we_freceive
tb_ahci.dut.sata_top.ahci_top_i.regs_we_acs
tb_ahci.dut.sata_top.ahci_top_i.regs_we
tb_ahci.dut.sata_top.ahci_top_i.regs_re[1:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_acs[31:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.regs_din_from_freceive[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.port_arst
tb_ahci.dut.sata_top.ahci_top_i.hba_arst
tb_ahci.dut.sata_top.ahci_top_i.phy_ready[1:0]
tb_ahci.dut.sata_top.ahci_top_i.irq
@800022
@c00022
tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
......@@ -129,13 +277,194 @@ tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.tfd_sts[7:0]
@23
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
@1001200
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_i
@1401200
-group_end
@1000200
-ahci_top
@800200
@c00200
-ahci_ctrl_stat
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_din[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_we
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_HBA_PORT__PxSERR
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_HBA_PORT__PxSSTS
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSERR_r[31:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0_clear
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci_changed
@800022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
@1001200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
@1401200
-group_end
@c00200
-ssts
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_det[3:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_det[3:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_det[3:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_det[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_det[3:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_ipm[11:8]
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sssts_spd[7:4]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_changed
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_det[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_det_dnp
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_det_dp
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_det_ndnp
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_det_offline
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_ipm_active
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_ipm_devsleep
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_ipm_dnp
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_ipm_part
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_ipm_slumb
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_dnp
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen1
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@1401200
-ssts
-ahci_ctrl_stat
@c00200
-axi_ahci_regs
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_reset_cntr[8:0]
......@@ -146,7 +475,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.port_arst_any
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wait_first_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@1000200
@1401200
-axi_ahci_regs
@800200
-ahci_fsm
......@@ -239,7 +568,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1000200
-ahci_fsm
@800200
@c00200
-link
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy_speed[1:0]
......@@ -280,6 +609,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1000200
-states
@1401200
-link
@800200
-phy
......
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