more debugging (f64d20dd) · Commits · Elphel / x393_sata

ahci/ahci_ctrl_stat.v

+3 −1

Original line number	Diff line number	Diff line
		@@ -225,7 +225,9 @@ module ahci_ctrl_stat #(
		reg sirq_changed;
		reg pxcmd_changed;
		reg ghc_is_changed;
		wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
		// wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
		wire [5:0] regs_changed={pxci_changed, pxcmd_changed, serr_changed, ssts_changed, sirq_changed,ghc_is_changed };

		// wire [5:0] update;
		reg [5:1] updating;
		wire [5:0] update_first = {6{update_all}} &

ahci/ahci_sata_layers.v

+12 −12

Original line number	Diff line number	Diff line
		@@ -178,20 +178,20 @@ module ahci_sata_layers #(
		//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair \| state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
		assign phy_speed = phy_ready ? PHY_SPEED:0;

		assign serr_DB = \|ph2ll_err_out;
		assign serr_DH = xmit_err;
		assign serr_DB = phy_ready && (\|ph2ll_err_out);
		assign serr_DH = phy_ready && (xmit_err);

		// not yet assigned errors
		assign serr_DT = 0; // RWC: Transport state transition error
		assign serr_DS = 0; // RWC: Link sequence error
		assign serr_DC = 0; // RWC: CRC error in Link layer
		assign serr_DB = 0; // RWC: 10B to 8B decode error
		assign serr_DI = 0; // RWC: PHY Internal Error
		assign serr_EP = 0; // RWC: Protocol Error - a violation of SATA protocol detected
		assign serr_EC = 0; // RWC: Persistent Communication or Data Integrity Error
		assign serr_ET = 0; // RWC: Transient Data Integrity Error (error not recovered by the interface)
		assign serr_EM = 0; // RWC: Communication between the device and host was lost but re-established
		assign serr_EI = 0; // RWC: Recovered Data integrity Error
		assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
		assign serr_DS = phy_ready && (0); // RWC: Link sequence error
		assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
		assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
		assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
		assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
		assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
		assign serr_ET = phy_ready && (0); // RWC: Transient Data Integrity Error (error not recovered by the interface)
		assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
		assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error

ahci/ahci_top.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -202,8 +202,8 @@ module ahci_top#(
		wire [ADDRESS_BITS-1:0] regs_raddr;
		wire [31:0] regs_din_from_freceive;
		wire [31:0] regs_dout;
		wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we}} & regs_waddr) \|
		({ADDRESS_BITS{regs_re[0]}} & regs_raddr) \|
		wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) \|
		({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) \|
		// ({ADDRESS_BITS{regs_re_fsm[0] \| regs_we_acs}} & regs_saddr);
		({ADDRESS_BITS{regs_we_acs}} & regs_saddr);

ahci/axi_ahci_regs.v

+28 −18

Original line number	Diff line number	Diff line
		@@ -151,7 +151,8 @@ module axi_ahci_regs#(
		reg write_busy_r;
		wire write_start_burst;
		// wire nowrite; // delay write in read-modify-write register accesses
		wire write_busy_w = write_busy_r \|\| write_start_burst;
		/// wire write_busy_w = write_busy_r \|\| write_start_burst;
		wire write_busy_w = write_busy_r \|\| write_start_burst \|\| bram_wen_r;
		reg [31:0] bram_wdata_r;
		reg [31:0] bram_rdata_r;
		// reg bram_wen_d;
		@@ -186,9 +187,14 @@ module axi_ahci_regs#(
		reg [2:0] arst_r = ~0; // previous state of arst
		reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
		wire any_access = bram_wen_r \|\| bram_ren[0];
		reg bram_ren0_r;
		wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // axibram_read does not mask bram_ren and bram_regen with dev_ready !


		// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
		assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
		// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
		assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);

		assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
		assign port_arst = port_rst_r; // port _reset by software
		assign port_arst_any = port_arst_any_r;
		@@ -197,13 +203,15 @@ module axi_ahci_regs#(


		always @(posedge aclk) begin
		bram_ren0_r <= bram_ren_w[0];

		if (arst) write_busy_r <= 0;
		else if (write_start_burst) write_busy_r <= 1;
		else if (!pre_bram_wen) write_busy_r <= 0;

		if (bram_wen) bram_wdata_r <= bram_wdata;

		if (bram_ren[1]) bram_rdata_r <= bram_rdata;
		if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;

		bram_wstb_r <= {4{bram_wen}} & bram_wstb;

		@@ -394,7 +402,9 @@ sata_phy_rst_out will be released after the sata clock is stable
		) ahci_regs_i (
		.clk_a (aclk), // input
		.addr_a (bram_addr), // input[9:0]
		.en_a (bram_ren[0] \|\| write_busy_w), // input
		/// .en_a (bram_ren[0] \|\| write_busy_w), // input
		/// .en_a (bram_ren[0] \|\| bram_wen \|\| bram_wen_r), // input
		.en_a (bram_ren_w[0] \|\| bram_wen \|\| bram_wen_r), // input
		.regen_a (1'b0), // input
		// .we_a (write_busy_r && !nowrite), // input
		.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]

tb/tb_ahci.tf

+21 −4

Original line number	Diff line number	Diff line
		@@ -626,6 +626,17 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
		end
		endtask

		task maxigp1_writep; // address in bytes, not words
		input [31:0] address;
		input [31:0] data;
		begin
		axi_write_single(address + MAXIGP1, data);
		$display ("%x <- %x @ %t",address + MAXIGP1, data,$time);
		end
		endtask



		task maxigp1_read;
		input [31:0] address;
		begin
		@@ -653,9 +664,15 @@ initial begin //Host
		axi_set_rd_lag(0);
		axi_set_b_lag(0);

		maxigp1_print(PCI_Header__CAP__CAP__ADDR);
		maxigp1_print(GHC__PI__PI__ADDR);
		maxigp1_print(HBA_PORT__PxCMD__ICC__ADDR);
		maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);
		maxigp1_print (GHC__PI__PI__ADDR << 2);
		maxigp1_print (HBA_PORT__PxCMD__ICC__ADDR << 2);
		maxigp1_print (GHC__GHC__IE__ADDR << 2);
		maxigp1_writep (GHC__GHC__IE__ADDR << 2, GHC__GHC__IE__MASK); // enable interrupts (global)
		maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);
		maxigp1_writep (HBA_PORT__PxIE__CPDE__ADDR << 2, ~0); // allow all interrupts
		maxigp1_print (GHC__GHC__IE__ADDR << 2);
		maxigp1_print (HBA_PORT__PxIE__CPDE__ADDR << 2);

		// $finish;

Admin message