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Commit f1e33691 authored by Andrey Filippov's avatar Andrey Filippov
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fixed more errors (single incoming HOLDP)

parent c2aaf658
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.project
View file @ f1e33691
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160306195310071.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160307105520276.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160306195310071.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160307105520276.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160306195735683.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160307105701067.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160306195310071.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160307105520276.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160306195735683.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160307105701067.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160306195735683.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160307105701067.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160306195735683.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160307105701067.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160306195735683.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160307105701067.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160306195735683.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160307105701067.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160306195310071.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160307105520276.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
device/sata_device.v
View file @ f1e33691
...@@ -874,7 +874,7 @@ task send_incrementing_data_pause; // @SuppressThisWarning VEditor - Used in tes ...@@ -874,7 +874,7 @@ task send_incrementing_data_pause; // @SuppressThisWarning VEditor - Used in tes
begin begin
clear_transmit_pause(0); clear_transmit_pause(0);
for (i=0;i<len;i=i+8) begin for (i=0;i<len;i=i+8) begin
transmit_data_pause[i+1] = i; // each 8-th have increainsg pause transmit_data_pause[i+1] = i / 8; // each 8-th have increainsg pause 1,2,3...
end end
transmit_data[0] = FIS_DATA; transmit_data[0] = FIS_DATA;
for (i=0;i<len;i=i+1) begin for (i=0;i<len;i=i+1) begin
......
generated/action_decoder.v
View file @ f1e33691
/******************************************************************************* /*******************************************************************************
* Module: action_decoder * Module: action_decoder
* Date:2016-03-03 * Date:2016-03-07
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions * Description: Decode sequencer code to 1-hot actions
*******************************************************************************/ *******************************************************************************/
......
generated/condition_mux.v
View file @ f1e33691
/******************************************************************************* /*******************************************************************************
* Module: condition_mux * Module: condition_mux
* Date:2016-03-03 * Date:2016-03-07
* Author: auto-generated file, see ahci_fsm_sequence.py * Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition * Description: Select condition
*******************************************************************************/ *******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ f1e33691
...@@ -141,8 +141,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -141,8 +141,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:NotRunning'}, { GOTO:'P:NotRunning'},
{LBL:'P:RegFisUpdate', ACT: 'GET_RFIS*'}, # get_rfis {LBL:'P:RegFisUpdate', ACT: 'GET_RFIS*'}, # get_rfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'P:RegFisAccept'}, { GOTO:'P:RegFisAccept'},
{LBL:'P:RegFisAccept', ACT: 'R_OK'}, # send R_OK {LBL:'P:RegFisAccept', ACT: 'R_OK'}, # send R_OK
...@@ -162,8 +162,11 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -162,8 +162,11 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'P:Offline', ACT: 'SET_OFFLINE'}, # set_offline {LBL:'P:Offline', ACT: 'SET_OFFLINE'}, # set_offline
{ ACT: 'SCTL_DET_CLEAR'}, # sctl_det_reset { ACT: 'SCTL_DET_CLEAR'}, # sctl_det_reset
{ GOTO:'P:NotRunning'}, { GOTO:'P:NotRunning'},
{LBL:'P:StartBitCleared', ACT: 'PXCI0_CLEAR'}, # pxci0_clear {LBL:'P:StartBitCleared', ACT: 'R_ERR'}, # While it forever loop after Fatal, LL may miss incoming FIS waiting for R_OK/R_ERR
# Maybe we need to check for that FIS, but for now just reject it (nothing will happen
# if LINK was not waiting for the R_OK/R_ERR)
{ ACT: 'PXCI0_CLEAR'}, # pxci0_clear
{ ACT: 'DMA_ABORT*'}, # dma_cmd_abort (should eventually clear PxCMD.CR)? { ACT: 'DMA_ABORT*'}, # dma_cmd_abort (should eventually clear PxCMD.CR)?
{ ACT: 'PCMD_CR_CLEAR'}, # pcmd_cr_reset { ACT: 'PCMD_CR_CLEAR'}, # pcmd_cr_reset
{ ACT: 'XFER_CNTR_CLEAR'}, # clear_xfer_cntr { ACT: 'XFER_CNTR_CLEAR'}, # clear_xfer_cntr
...@@ -209,18 +212,18 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -209,18 +212,18 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'NDR:Entry', ACT: 'NOP'}, {LBL:'NDR:Entry', ACT: 'NOP'},
# {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err # {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
# {IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr # {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'NDR:Accept'}, # 4. { GOTO:'NDR:Accept'}, # 4.
{LBL:'NDR:IgnoreNR', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO {LBL:'NDR:IgnoreNR', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'P:OkIdle'}, # { GOTO:'P:OkIdle'}, #
{LBL:'NDR:IgnoreIdle', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO {LBL:'NDR:IgnoreIdle', ACT: 'GET_IGNORE*'}, # get_ignore This one is not in docs, just to empty FIS FIFO
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'P:OkNotRunning'}, # { GOTO:'P:OkNotRunning'}, #
...@@ -279,8 +282,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -279,8 +282,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'PIO:Update'}, # 2. { GOTO:'PIO:Update'}, # 2.
#5.3.8 D2H Register FIS Receive States #5.3.8 D2H Register FIS Receive States
{LBL:'RegFIS:Entry', ACT: 'GET_RFIS*'}, # get_rfis {LBL:'RegFIS:Entry', ACT: 'GET_RFIS*'}, # get_rfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'RegFIS:Accept'}, # { GOTO:'RegFIS:Accept'}, #
{LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'RegFIS:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -306,8 +309,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -306,8 +309,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#RegFIS:SetSig skipped, done in RegFIS:UpdateSig #RegFIS:SetSig skipped, done in RegFIS:UpdateSig
#5.3.9 PIO Setup Receive States #5.3.9 PIO Setup Receive States
{LBL:'PIO:Entry', ACT: 'GET_PSFIS*'}, # get_psfis, includes all steps 1..9 {LBL:'PIO:Entry', ACT: 'GET_PSFIS*'}, # get_psfis, includes all steps 1..9
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'PIO:Accept' }, { GOTO:'PIO:Accept' },
{LBL:'PIO:Accept', ACT: 'R_OK'}, # get_psfis, includes all steps 1..9 {LBL:'PIO:Accept', ACT: 'R_OK'}, # get_psfis, includes all steps 1..9
...@@ -336,8 +339,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -336,8 +339,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#PIO:SetIS, PIO:GenIntr are handled by hardware, skipping #PIO:SetIS, PIO:GenIntr are handled by hardware, skipping
#5.3.10 Data Transmit States #5.3.10 Data Transmit States
{LBL:'DX:EntryIgnore', ACT: 'GET_IGNORE*'}, # Read/Ignore FIS in FIFO (not in docs) {LBL:'DX:EntryIgnore', ACT: 'GET_IGNORE*'}, # Read/Ignore FIS in FIFO (not in docs)
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'DX:Accept'}, # { GOTO:'DX:Accept'}, #
{LBL:'DX:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'DX:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -369,10 +372,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -369,10 +372,10 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'DR:Receive'}, { GOTO:'DR:Receive'},
{LBL:'DR:Receive', ACT: 'GET_DATA_FIS*'}, # get_data_fis {LBL:'DR:Receive', ACT: 'GET_DATA_FIS*'}, # get_data_fis
{IF: 'FIS_ERR', GOTO:'ERR:Fatal_R_ERR'}, # 3. fis_err - checking for errors first to give some time for fis_extra {IF: 'FIS_ERR', GOTO:'ERR:Fatal'}, # 3. fis_err - checking for errors first to give some time for fis_extra
# to reveal itself from the ahci_dma module (ahci_fis_receive does not need it) # to reveal itself from the ahci_dma module (ahci_fis_receive does not need it)
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 3a. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 3a. fis_ferr
{IF: 'FIS_EXTRA', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_extra {IF: 'FIS_EXTRA', GOTO:'ERR:Non-Fatal'}, # 1. fis_extra
{ GOTO:'DR:UpdateByteCount'}, # 2. fis_ok implied { GOTO:'DR:UpdateByteCount'}, # 2. fis_ok implied
{LBL:'DR:UpdateByteCount', ACT: 'R_OK'}, # send_R_OK to device {LBL:'DR:UpdateByteCount', ACT: 'R_OK'}, # send_R_OK to device
...@@ -384,8 +387,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -384,8 +387,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
# 5.3.12 DMA Setup Receive States # 5.3.12 DMA Setup Receive States
{LBL:'DmaSet:Entry', ACT: 'GET_DSFIS*'}, # get_dsfis {LBL:'DmaSet:Entry', ACT: 'GET_DSFIS*'}, # get_dsfis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'DmaSet:Accept'}, # { GOTO:'DmaSet:Accept'}, #
{LBL:'DmaSet:Accept', ACT: 'R_OK'}, # send R_OK {LBL:'DmaSet:Accept', ACT: 'R_OK'}, # send R_OK
...@@ -400,8 +403,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -400,8 +403,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:Idle' }, # 3. { GOTO:'P:Idle' }, # 3.
#5.3.13 Set Device Bits States #5.3.13 Set Device Bits States
{LBL:'SDB:Entry', ACT: 'GET_SDBFIS*'}, # get_sdbfis Is in only for Native CC ? {LBL:'SDB:Entry', ACT: 'GET_SDBFIS*'}, # get_sdbfis Is in only for Native CC ?
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'SDB:Accept' }, # 3. { GOTO:'SDB:Accept' }, # 3.
{LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ? {LBL:'SDB:Accept', ACT: 'R_OK'}, # get_sdbfis Is in only for Native CC ?
...@@ -417,8 +420,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -417,8 +420,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'PM:Aggr' }, # 5. { GOTO:'PM:Aggr' }, # 5.
#5.3.14 Unknown FIS Receive States #5.3.14 Unknown FIS Receive States
{LBL:'UFIS:Entry', ACT: 'GET_UFIS*'}, # get_ufis {LBL:'UFIS:Entry', ACT: 'GET_UFIS*'}, # get_ufis
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'UFIS:Accept' }, # { GOTO:'UFIS:Accept' }, #
{LBL:'UFIS:Accept', ACT: 'R_OK'}, # get_ufis {LBL:'UFIS:Accept', ACT: 'R_OK'}, # get_ufis
...@@ -428,8 +431,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -428,8 +431,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
#5.3.15 BIST States #5.3.15 BIST States
{LBL:'BIST:FarEndLoopback', ACT: 'GET_IGNORE*'}, # get_ignore {LBL:'BIST:FarEndLoopback', ACT: 'GET_IGNORE*'}, # get_ignore
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'BIST:FarEndLoopbackAccept'}, # 1. (IRQ states are handled) { GOTO:'BIST:FarEndLoopbackAccept'}, # 1. (IRQ states are handled)
{LBL:'BIST:FarEndLoopbackAccept', ACT: 'R_OK'}, # send R_OK {LBL:'BIST:FarEndLoopbackAccept', ACT: 'R_OK'}, # send R_OK
...@@ -437,8 +440,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -437,8 +440,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'BIST:TestLoop'}, # 1. { GOTO:'BIST:TestLoop'}, # 1.
{LBL:'BIST:TestOngoing', ACT: 'GET_IGNORE*'}, # get_ignore {LBL:'BIST:TestOngoing', ACT: 'GET_IGNORE*'}, # get_ignore
{IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal_R_ERR'}, # 1. fis_err {IF: 'FIS_ERR', GOTO:'ERR:Non-Fatal'}, # 1. fis_err
{IF: 'FIS_FERR', GOTO:'ERR:Fatal_R_ERR'}, # 2. fis_ferr {IF: 'FIS_FERR', GOTO:'ERR:Fatal'}, # 2. fis_ferr
{ GOTO:'BIST:TestLoopAccept'}, # { GOTO:'BIST:TestLoopAccept'}, #
{LBL:'BIST:TestLoopAccept', ACT: 'R_OK'}, # {LBL:'BIST:TestLoopAccept', ACT: 'R_OK'}, #
...@@ -451,22 +454,19 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -451,22 +454,19 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ ACT: 'SIRQ_IF'}, # sirq_IF { ACT: 'SIRQ_IF'}, # sirq_IF
{ GOTO:'ERR:WaitForClear' }, { GOTO:'ERR:WaitForClear' },
{LBL:'ERR:Fatal_R_ERR', ACT: 'R_ERR'}, # Send 'R_ERR' to device. SATA sais it should be Transport L, AHCI - Link L
{ GOTO:'ERR:Fatal' }, #
{LBL:'ERR:Fatal', ACT: 'SIRQ_IF'}, # sirq_IF {LBL:'ERR:Fatal', ACT: 'R_ERR'}, # Link layer auto-sends R_ERR on CRC, but extra request won't hurt (it will be ignored)
{ ACT: 'SIRQ_IF'}, # sirq_IF
{ GOTO:'ERR:WaitForClear' }, { GOTO:'ERR:WaitForClear' },
{LBL:'ERR:FatalTaskfile', ACT: 'SIRQ_TFE'}, # sirq_TFE {LBL:'ERR:FatalTaskfile', ACT: 'SIRQ_TFE'}, # sirq_TFE #R_OK already sent
{ GOTO:'ERR:WaitForClear' }, { GOTO:'ERR:WaitForClear' },
{LBL:'ERR:WaitForClear', ACT: 'NOP'}, # {LBL:'ERR:WaitForClear', ACT: 'NOP'}, #
{ GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software { GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software
{LBL:'ERR:Non-Fatal_R_ERR', ACT: 'R_ERR'}, # Send 'R_ERR' to device. SATA says it should be Transport L, AHCI - Link L {LBL:'ERR:Non-Fatal', ACT: 'R_ERR'}, # Link layer auto-sends R_ERR on CRC, but extra request won't hurt (it will be ignored)
{ GOTO:'ERR:Non-Fatal' }, # { ACT: 'SIRQ_INF'}, # sirq_INF
{LBL:'ERR:Non-Fatal', ACT: 'SIRQ_INF'}, # sirq_INF
{ GOTO:'P:Idle'}, # { GOTO:'P:Idle'}, #
] ]
def get_cnk (start,end,level): def get_cnk (start,end,level):
......
host/link.v
View file @ f1e33691
...@@ -77,7 +77,8 @@ module link #( ...@@ -77,7 +77,8 @@ module link #(
output wire incom_invalidate, // if incoming transition had errors output wire incom_invalidate, // if incoming transition had errors
output wire incom_sync_escape, // particular type - got sync escape output wire incom_sync_escape, // particular type - got sync escape
input wire incom_ack_good, // transport layer responds on a completion of a FIS input wire incom_ack_good, // transport layer responds on a completion of a FIS
input wire incom_ack_bad, input wire incom_ack_bad, // Reject frame even if it had good CRC (Bad will be responded automatically)
// It is OK to send extra incom_ack_bad from transport - it will be discarded
input wire link_reset, // oob sequence is reinitiated and link now is not established or rxelecidle input wire link_reset, // oob sequence is reinitiated and link now is not established or rxelecidle
input wire sync_escape_req, // TL demands to brutally cancel current transaction input wire sync_escape_req, // TL demands to brutally cancel current transaction
output wire sync_escape_ack, // acknowlegement of a successful reception output wire sync_escape_ack, // acknowlegement of a successful reception
...@@ -416,12 +417,13 @@ assign set_rcvr_data = state_rcvr_rdy & dword_val & rcvd_dword[COD ...@@ -416,12 +417,13 @@ assign set_rcvr_data = state_rcvr_rdy & dword_val & rcvd_dword[COD
// | state_rcvr_rhold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP] & ~data_busy_in // | state_rcvr_rhold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP] & ~data_busy_in
| state_rcvr_rhold & next_will_be_data & ~data_busy_in | state_rcvr_rhold & next_will_be_data & ~data_busy_in
// | state_rcvr_shold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP]; // | state_rcvr_shold & dword_val_na & ~rcvd_dword[CODE_HOLDP] & ~rcvd_dword[CODE_EOFP] & ~rcvd_dword[CODE_SYNCP];
| state_rcvr_shold & next_will_be_data; // So it will not be align | state_rcvr_shold & next_will_be_data // So it will not be align
| state_rcvr_data & next_will_be_data; // to skip over single-cycle CODE_HOLDP
//next_will_be_data //next_will_be_data
assign set_rcvr_rhold = state_rcvr_data & dword_val & rcvd_dword[CODE_DATA] & data_busy_in; assign set_rcvr_rhold = state_rcvr_data & dword_val & rcvd_dword[CODE_DATA] & data_busy_in;
assign set_rcvr_shold = state_rcvr_data & dword_val & rcvd_dword[CODE_HOLDP] assign set_rcvr_shold = state_rcvr_data & dword_val & (rcvd_dword[CODE_HOLDP] & ~next_will_be_data)
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_HOLDP] & ~data_busy_in; | state_rcvr_rhold & dword_val & (rcvd_dword[CODE_HOLDP] & ~next_will_be_data) & ~data_busy_in;
assign set_rcvr_eof = state_rcvr_data & dword_val & rcvd_dword[CODE_EOFP] assign set_rcvr_eof = state_rcvr_data & dword_val & rcvd_dword[CODE_EOFP]
| state_rcvr_rhold & dword_val & rcvd_dword[CODE_EOFP] | state_rcvr_rhold & dword_val & rcvd_dword[CODE_EOFP]
...@@ -431,9 +433,9 @@ assign set_rcvr_goodcrc = state_rcvr_eof & crc_good; ...@@ -431,9 +433,9 @@ assign set_rcvr_goodcrc = state_rcvr_eof & crc_good;
assign set_rcvr_goodend = state_rcvr_goodcrc& incom_ack_good_or_pend; // incom_ack_good; // may arrive at aligns_pair assign set_rcvr_goodend = state_rcvr_goodcrc& incom_ack_good_or_pend; // incom_ack_good; // may arrive at aligns_pair
assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP] assign set_rcvr_badend = state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP] // Missed EOF
| state_rcvr_eof & crc_bad | state_rcvr_eof & crc_bad // Got bad CRC
| state_rcvr_goodcrc& incom_ack_bad_or_pend; // incom_ack_bad; // may arrive at aligns_pair | state_rcvr_goodcrc& incom_ack_bad_or_pend; // incom_ack_bad; // Transport didn't like it (may arrive at aligns_pair)
assign clr_sync_esc = set_nocommerr | set_reset | dword_val & (rcvd_dword[CODE_RRDYP] | rcvd_dword[CODE_SYNCP]); assign clr_sync_esc = set_nocommerr | set_reset | dword_val & (rcvd_dword[CODE_RRDYP] | rcvd_dword[CODE_SYNCP]);
assign clr_nocommerr = set_reset | set_nocomm; assign clr_nocommerr = set_reset | set_nocomm;
......
includes/ahxi_fsm_code.vh
View file @ f1e33691
, .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000) , .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000)
, .INIT_01 (256'h1C3B9448543244190060001B0108001B00500402040401040022000600120000) , .INIT_01 (256'h1C3B9448543244190060001B0108001B00500402040401040022000600120000)
, .INIT_02 (256'h001BC8300014000C0210002B2506250E0180001B0003004200180000001B4454) , .INIT_02 (256'h001BC8300014000C0210002B2506250D0180001B0003004200180000001B4454)
, .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005) , .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005)
, .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C00A0003B8C6D845484C6) , .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C00A0003B8C6D845484C6)
, .INIT_05 (256'h045A000000502506250E0240004E2506250E0240005E0000003B0000001B0210) , .INIT_05 (256'h045A000000502506250D0240004E2506250D0240005E0000003B0000001B0210)
, .INIT_06 (256'h903B02200204006D0402009000EDA89868FB18F418D398AF58DF388464560C27) , .INIT_06 (256'h903B02200204006D0402009000EDA89868FB18F418D398AF58DF388464560C27)
, .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930FB02080073D1105103) , .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930FB02080073D10D5103)
, .INIT_08 (256'h00962890290A0000000000000014021000882506250E018000A1D1080120003B) , .INIT_08 (256'h0096289029090000000000000014021000882506250D018000A1D1060120003B)
, .INIT_09 (256'h48810CB5290A0210009C2506250E04400052000C009600050096C89400220044) , .INIT_09 (256'h48810CB529090210009C2506250D04400052000C009600050096C89400220044)
, .INIT_0A (256'h024000520081005248AD00220044003B48AD28A9290A0000000000000024003B) , .INIT_0A (256'h024000520081005248AD00220044003B48AD28A929090000000000000024003B)
, .INIT_0B (256'h50C20044008800BDD1085103042000B9883B08A1003000B5021000B32506250E) , .INIT_0B (256'h50C20044008800BDD1065103042000B9883B08A1003000B5021000B32506250D)
, .INIT_0C (256'h00440048021000CDC50E2506250600C000C80030003B88A100300009003B88A1) , .INIT_0C (256'h00440048021000CDC50D2506250600C000C80030003B88A100300009003B88A1)
, .INIT_0D (256'h0280003B34DA000000DC001100DCC8DA021000D72506250E0140003B88A150C2) , .INIT_0D (256'h0280003B34DA000000DC001100DCC8DA021000D72506250D0140003B88A150C2)
, .INIT_0E (256'h2506250E0480005201010052C8EB290A0000000000000014021000E32506250E) , .INIT_0E (256'h2506250D0480005201010052C8EB29090000000000000014021000E32506250D)
, .INIT_0F (256'h021000FF2506250E024001010082021000F82506250E0240003B0401021000F1) , .INIT_0F (256'h021000FF2506250D024001010082021000F82506250D0240003B0401021000F1)
, .INIT_10 (256'h01100410010C0000010C0201010C002101080410010C00210084010100000101) , .INIT_10 (256'h003B00410410010B0000010B0201010B00210410010B00210084010100000101)
, .INIT_11 (256'h00000000000000000000000000000000000000000000000000000000003B0041)
, .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222) , .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222)
, .INITP_01 (256'h89C827209C828009C22089C680272181A01CB889C8605A00AA2722081A00270C) , .INITP_01 (256'h89C827209C828009C22089C680272181A01CB889C8605A00AA2722081A00270C)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000222222208) , .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000020888208)
py393sata/x393sata.py
View file @ f1e33691
...@@ -1529,10 +1529,10 @@ sata.vsc3304.PCB_CONNECTIONS['10389B']['INVERTED_PORTS'] ...@@ -1529,10 +1529,10 @@ sata.vsc3304.PCB_CONNECTIONS['10389B']['INVERTED_PORTS']
('A', 'E', 'G', 'H') ('A', 'E', 'G', 'H')
sata.vsc3304.PCB_CONNECTIONS['10389B']['INVERTED_PORTS']=('E','G','H') sata.vsc3304.PCB_CONNECTIONS['10389B']['INVERTED_PORTS']=('E','G','H')
#######################################
reload (x393sata) reload (x393sata)
sata = x393sata.x393sata() sata = x393sata.x393sata()
#######################################
cd /mnt/mmc/local/bin cd /mnt/mmc/local/bin
python python
from __future__ import print_function from __future__ import print_function
...@@ -1541,6 +1541,8 @@ import x393sata ...@@ -1541,6 +1541,8 @@ import x393sata
import x393_mem import x393_mem
mem = x393_mem.X393Mem(1,0,1) mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata() # 1,0,"10389B") sata = x393sata.x393sata() # 1,0,"10389B")
sata.reinit_mux() sata.reinit_mux()
sata.bitstream() sata.bitstream()
...@@ -1554,6 +1556,7 @@ sata.drp (0x59,0x8) # Use RXREC ...@@ -1554,6 +1556,7 @@ sata.drp (0x59,0x8) # Use RXREC
#sata.drp (0x59,0x48) #sata.drp (0x59,0x48)
sata.reg_status() sata.reg_status()
sata.reg_status() sata.reg_status()
#need to sleep here !!
sata.arm_logger() sata.arm_logger()
......
tb_ahci_01.sav
View file @ f1e33691
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Mar 7 02:46:09 2016 [*] Mon Mar 7 17:54:44 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160306192631093.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160307105210141.fst"
[dumpfile_mtime] "Mon Mar 7 02:28:25 2016" [dumpfile_mtime] "Mon Mar 7 17:54:09 2016"
[dumpfile_size] 14586310 [dumpfile_size] 15120516
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 33393100 [timestart] 32540300
[size] 1823 1180 [size] 1817 609
[pos] 1920 60 [pos] 1923 0
*-16.114683 33642778 32476228 47988010 32736600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-16.022064 32722870 32476228 47988010 32736600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev. [treeopen] tb_ahci.dev.
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
[sst_width] 252 [sst_width] 252
[signals_width] 349 [signals_width] 349
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 577 [sst_vpaned_height] 259
@820 @820
tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
...@@ -4067,7 +4067,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0] ...@@ -4067,7 +4067,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
-group_end -group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.next_will_be_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.next_will_be_data
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_data
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_shold tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold
...@@ -4193,6 +4195,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend ...@@ -4193,6 +4195,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend
@1000200 @1000200
-states -states
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.got_escape
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_align tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_nocommerr tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_nocommerr
...@@ -4642,7 +4646,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detec ...@@ -4642,7 +4646,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detec
- -
@1401200 @1401200
-comma -comma
@c00201 @c00200
-elastic_phy -elastic_phy
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_phy0[31:0]
...@@ -4694,7 +4698,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.inc_waddr ...@@ -4694,7 +4698,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.inc_waddr
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.waddr[4:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.waddr[4:0]
@200 @200
- -
@1401201 @1401200
-elastic_phy -elastic_phy
@c00200 @c00200
-elastic_slow -elastic_slow
......
x393_sata.bit
View file @ f1e33691
No preview for this file type
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