Skip to content

X
x393_sata
Commit f1b706b5 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

more testing

parent d5b58b3a
Hide whitespace changes
Inline Side-by-side
Showing with 245 additions and 69 deletions
.project
View file @ f1b706b5
......@@ -52,87 +52,87 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160130150815853.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160130150815853.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160130001427345.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160122012249330.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160130150815853.log</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160130001427345.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160130001427345.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160130001427345.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160130001427345.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160130001427345.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160122012249330.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160130150815853.dcp</location>
</link>
</linkedResources>
</projectDescription>
ahci/ahci_sata_layers.v
View file @ f1b706b5
......@@ -120,9 +120,10 @@ module ahci_sata_layers #(
reg [1:0] d2h_type_in;
reg fis_over_r; // push 1 more DWORD (ignore) + type (ERR/OK) when received FIS is done/error
wire ll_frame_req_w; // pre ll_frame_req
// wire ll_frame_req_w; // pre ll_frame_req
reg ll_frame_req; // -> link // request for a new frame transition
wire ll_frame_busy; // link -> // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
wire ll_frame_ackn; // acknowledge for ll_frame_req
// wire ll_frame_busy; // link -> // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
// wire ll_frame_ack; // link -> // LL tells if the request is transmitting not used
// wire ll_frame_rej; // link -> // or if it was cancelled because of simultanious incoming transmission
// wire ll_frame_done_good; // link -> // TL tell if the outcoming transaction is done and how it was done
......@@ -173,7 +174,7 @@ module ahci_sata_layers #(
assign h2d_ready = !h2d_fill[FIFO_ADDR_WIDTH] && !(&h2d_fill[FIFO_ADDR_WIDTH:3]);
assign ll_d2h_almost_full = d2h_fill[FIFO_ADDR_WIDTH] || &d2h_fill[FIFO_ADDR_WIDTH-1:6]; // 63 dwords (maybe use :5?) - time to tell device to stop
assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));
// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits
//assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data & dword_val & rcvd_dword[CODE_WTRMP];
assign phy_speed = phy_ready ? PHY_SPEED:0;
......@@ -185,7 +186,7 @@ module ahci_sata_layers #(
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
assign serr_EC = phy_ready && (0); // RWC: Persistent Communication or Data Integrity Error
......@@ -216,8 +217,8 @@ module ahci_sata_layers #(
.data_last_out (), // ll_d2h_last), // output wire not used
.frame_req (ll_frame_req), // input wire // request for a new frame transmission
.frame_busy (ll_frame_busy), // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
.frame_ack (), // ll_frame_ack), // output wire // LL tells if the request is transmitting
.frame_busy (), // ll_frame_busy), // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
.frame_ack (ll_frame_ackn), // ll_frame_ack), // output wire // LL tells if the request is transmitting
.frame_rej (x_rdy_collision), // output wire // or if it was cancelled because of simultanious incoming transmission
.frame_done_good (xmit_ok), // output wire // TL tell if the outcoming transaction is done and how it was done
.frame_done_bad (xmit_err), // output wire
......@@ -259,8 +260,12 @@ module ahci_sata_layers #(
if (rst || ll_frame_req) h2d_pending <= 0;
else if ((h2d_type == H2D_TYPE_FIS_HEAD) && h2d_fifo_wr) h2d_pending <= 1;
if (rst) ll_frame_req <= 0;
else ll_frame_req <= ll_frame_req_w;
if (rst) ll_frame_req <= 0;
// else ll_frame_req <= ll_frame_req_w;
else if (h2d_pending &&
(((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) ||
(|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]))) ll_frame_req <= 1;
else if (ll_frame_ackn) ll_frame_req <= 0;
end
......
device/sata_device.v
View file @ f1b706b5
......@@ -126,6 +126,7 @@ integer suppress_receive = 0;
reg [31:0] receive_data [2047:0];
reg [31:0] receive_data_pause [2047:0];
integer received_size; // number of data FIS payload dwords received (minus head and CRC)
reg [31:0] receive_wait_fifo;
reg [31:0] receive_crc;
integer receive_id = 0;
......@@ -133,6 +134,7 @@ integer receive_status = 0;
/*
* Monitor incoming primitives every clock cycle
* if there is a data transfer request, start a receive sequence
......@@ -358,6 +360,7 @@ task linkMonitorFIS;
if (~phy_ready) begin
DEV_TITLE = "Unexpected line disconnect #1";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim != "XRDY") begin
......@@ -365,6 +368,7 @@ task linkMonitorFIS;
DEV_TITLE = "Reception terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
......@@ -375,6 +379,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #2";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim != "XRDY") begin
......@@ -382,6 +387,7 @@ task linkMonitorFIS;
DEV_TITLE = "Reception terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
linkSendPrim("RRDY");
......@@ -396,14 +402,35 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #3";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim != "XRDY") begin
if (rprim == "ALIGN") begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #3";
DEV_TITLE = "Got ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
$finish;
@ (posedge clk)
rprim = linkGetPrim(0);
if (rprim != "ALIGN") begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
DEV_TITLE = "Was expecting another ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d got primitive = %s @%t", DEV_TITLE, DEV_DATA, rprim, $time);
#100;
$finish;
end else begin
DEV_TITLE = "Got second ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end
end
if ((rprim != "XRDY") && (rprim != "ALIGN")) begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
DEV_TITLE = "Reception terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d, rprim = %s @%t", DEV_TITLE, DEV_DATA, rprim, $time);
// #100;
// $finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
......@@ -413,6 +440,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #4";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
// $display("[Device] LINK: Detected Start of FIS");
......@@ -427,6 +455,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #5";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -434,6 +463,7 @@ task linkMonitorFIS;
DEV_TITLE = "Reception terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "SCRAP") begin
......@@ -441,13 +471,13 @@ task linkMonitorFIS;
DEV_TITLE = "Bad primitives from the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "EOF") begin
// $display("[Device] LINK: Detected End of FIS");
DEV_TITLE = "Detected End of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_stop = 1;
end
else
......@@ -499,6 +529,7 @@ task linkMonitorFIS;
DEV_TITLE = "Wrong data dwords count received";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if (cnt >= dmat_index) begin
......@@ -527,13 +558,14 @@ task linkMonitorFIS;
// $display("[Device] LINK: Incorrect number of received words");
DEV_TITLE = "Incorrect number of received words";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
// $display("[Device] LINK: Running CRC after all data was received = %h", crc);
DEV_TITLE = "Running CRC after all data was received";
DEV_DATA = crc;
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
received_size = cnt - 2; // data payload size in DWORDs
// if (crc != 32'h88c21025) begin // running disparity when data crc matches actual received crc
if (!crc_match) begin // running disparity when data crc matches actual received crc
// $display("[Device] LINK: Running CRC check failed");
......@@ -552,7 +584,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #6";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -560,7 +592,7 @@ task linkMonitorFIS;
DEV_TITLE = "Reception terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -568,6 +600,7 @@ task linkMonitorFIS;
DEV_TITLE = "Bad primitives from the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
......@@ -577,6 +610,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #7";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -584,6 +618,7 @@ task linkMonitorFIS;
DEV_TITLE = "Reception terminated by the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -591,6 +626,7 @@ task linkMonitorFIS;
DEV_TITLE = "Bad primitives from the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (tranCheckFIS(cnt - 1)) begin
......@@ -618,6 +654,7 @@ task linkMonitorFIS;
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #8";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -625,6 +662,7 @@ task linkMonitorFIS;
DEV_TITLE = "Bad primitives from the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
......@@ -673,13 +711,38 @@ task wait_ready; // @SuppressThisWarning VEditor - Used in testbench
end
endtask
/*
task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input [2:0] dev_specific_status_bits;
input irq;
output integer status;
begin
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
transmit_data[1] = 1;
transmit_data[2] = 0;
transmit_data[3] = 1;
transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status);
end
endtask
*/
task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input [2:0] dev_specific_status_bits;
input irq;
output integer status;
begin
send_D2HR(id,
irq,
{1'b0,dev_specific_status_bits,4'b0}, // status
1, // error
0, // device
0, // lba_low
0, // lba_high
0, // count
status); // output: result status
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
transmit_data[1] = 1;
transmit_data[2] = 0;
......@@ -689,6 +752,29 @@ task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
end
endtask
task send_D2HR; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input irq;
input [7:0] sts;
input [7:0] error;
input [7:0] device;
input [23:0] lba_low;
input [23:0] lba_high;
input [15:0] count;
output integer status;
begin
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (sts << 16) | (error << 24);
transmit_data[1] = {device,lba_low};
transmit_data[2] = {8'b0, lba_high};
transmit_data[3] = {16'b0,count};
transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status);
end
endtask
task send_pio_setup; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input d2h; // 'D' bit: 1 - Data will be D2H, 0 - H2D
......@@ -800,6 +886,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #9";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
@ (posedge clk)
......@@ -816,6 +903,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #10";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -823,6 +911,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -830,6 +919,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Bad primitives from the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_SendData + L_RcvrHold + L_SendHold
......@@ -852,6 +942,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -859,6 +950,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Bad primitives from the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
else
......@@ -867,6 +959,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the hostvia DMAT";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
else
......@@ -908,6 +1001,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #11";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -915,6 +1009,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -922,6 +1017,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Bad primitives from the host #7";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_SendEOF
......@@ -935,6 +1031,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #12";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -942,6 +1039,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -949,6 +1047,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Bad primitives from the host #8";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_Wait
......@@ -964,6 +1063,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
//$display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #13";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
......@@ -971,6 +1071,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
......@@ -978,6 +1079,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Bad primitives from the host #9";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "ERR") begin
......
host/link.v
View file @ f1b706b5
......@@ -35,7 +35,8 @@
//`include "crc.v"
module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4
parameter DATA_BYTE_WIDTH = 4,
parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs
)
(
// TODO insert watchdogs
......@@ -119,6 +120,7 @@ module link #(
reg [639:0] HOST_LINK_TITLE; // to show human-readable state in the GTKWave
reg [31:0] HOST_LINK_DATA;
`endif
// latching data-primitives stream from phy
reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;
reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r; // charisk
......@@ -188,9 +190,13 @@ end
reg data_txing; // if there are still some data to transmit and the transaction wasn't cancelled
always @ (posedge clk)
data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
always @ (posedge clk) begin
/// data_txing <= rst | (data_last_in & data_strobe_out | dword_val & rcvd_dword[CODE_DMATP]) ? 1'b0 : frame_req ? 1'b1 : data_txing;
if (rst ||
(data_last_in && data_strobe_out) ||
(dword_val && rcvd_dword[CODE_DMATP])) data_txing <= 0;
else if (frame_req) data_txing <= 1;
end
// fsm
// states and transitions are taken from the doc, "Link Layer State Machine" chapter
// power mode states are not implemented. TODO insert them as an additional branch of fsm
......@@ -293,25 +299,40 @@ assign state_idle = ~state_sync_esc
& ~state_rcvr_goodend
& ~state_rcvr_badend;
// got an escaping primitive = request to cancel the transmission
wire got_escape;
assign got_escape = dword_val & rcvd_dword[CODE_SYNCP];
// escaping is done
assign sync_escape_ack = state_sync_esc;
wire alignes_pair; // pauses every state go give a chance to insert 2 align primitives on a line at least every 256 dwords due to spec
wire alignes_pair_0; // time for 1st align primitive
wire alignes_pair_1; // time for 2nd align primitive
//wire alignes_pair_0; // time for 1st align primitive
//wire alignes_pair_1; // time for 2nd align primitive
reg [8:0] alignes_timer;
assign alignes_pair_0 = alignes_timer == 9'd252;
assign alignes_pair_1 = alignes_timer == 9'd253;
assign alignes_pair = alignes_pair_0 | alignes_pair_1;
always @ (posedge clk)
alignes_timer <= rst | alignes_pair_1 | state_reset ? 9'h0 : alignes_timer + 1'b1;
///assign alignes_pair_0 = alignes_timer == 9'd252;
///assign alignes_pair_1 = alignes_timer == 9'd253;
///assign alignes_pair_0 = alignes_timer == 9'd254;
///assign alignes_pair_1 = alignes_timer == 9'd255;
///always @ (posedge clk)
/// alignes_timer <= rst | alignes_pair_1 | state_reset ? 9'h0 : alignes_timer + 1'b1;
wire got_escape;
assign got_escape = dword_val & rcvd_dword[CODE_SYNCP];
// escaping is done
assign sync_escape_ack = state_sync_esc;
//select_prim[CODE_ALIGNP]
//ALIGNES_PERIOD
reg alignes_pair_0; // time for 1st align primitive
reg alignes_pair_1; // time for 2nd align primitive
always @ (posedge clk) begin
if (rst || select_prim[CODE_ALIGNP]) alignes_timer <= ALIGNES_PERIOD;
else alignes_timer <= alignes_timer -1;
alignes_pair_0 <= alignes_timer == 0;
alignes_pair_1 <= alignes_pair_0;
end
assign alignes_pair = alignes_pair_0 | alignes_pair_1;
// Whole transitions table, literally from doc pages 311-328
......
host/sata_phy.v
View file @ f1b706b5
......@@ -250,7 +250,7 @@ always @ (posedge clk or posedge extrst)
// else rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;
///assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;
*/
always @ (posedge clk or sata_areset) begin
always @ (posedge clk or posedge sata_areset) begin
if (sata_areset) sata_reset_done_r <= 0;
else sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};
end
......
tb/tb_ahci.tf
View file @ f1b706b5
......@@ -966,16 +966,26 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR");
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ);
// sysmem_print ('h1e81,'h180); // for shifted
sysmem_print ('h1e80,'h180);
sysmem_print ('h1e80,'h180); // Compact dump of "system memory" in hex word format
// Prepare for D2H register FIS with interrupt bit set (expected to be sent after all data will be written to the device)
maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear DHR (D2H register FIS with "I" bit) interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one)
wait (~IRQ);
setup_dma_write_identify_command_multi4(1,'h123456, 27,71,83); // LBA = 'h123456
TESTBENCH_TITLE = "Set DMA Write command for device";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
wait (IRQ);
TESTBENCH_TITLE = "DMA transfer to device completed";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
repeat (50) @(posedge CLK);
// $finish;
$finish;
//HBA_PORT__PxIE__DHRE__MASK = 'h1;
end
......@@ -993,6 +1003,13 @@ function func_is_dev_dma_write;
end
endfunction
function func_is_h2d_data;
input [31:0] dw;
begin
func_is_h2d_data = (dw & 'hff) == FIS_DATA ;
end
endfunction
integer status;
initial begin //Device
dev.clear_transmit_pause(0);
......@@ -1003,7 +1020,7 @@ initial begin //Device
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
dev.send_good_status (66, // input integer id;
5, // input [2:0] dev_specific_status_bits;
1, // input irq;
1, // IRQ
status); // output integer status;
DEVICE_TITLE = "Device sent D2H FIS";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
......@@ -1039,6 +1056,21 @@ initial begin //Device
dev.send_dma_activate (69, // input integer id;
status); // output integer status;
end else if (func_is_h2d_data(dev.receive_data[0])) begin
DEVICE_TITLE = "Got H2D data";
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
$display("[Dev-TB]: %hh payload DWORDs got (%d bytes) @%t", dev.received_size, dev.received_size << 2, $time);
// Assuming device got what it needed, otherwise send DMA Activate again
dev.send_D2HR(70,
1, // irq,
8'h0, // status
0, // error
0, // device
0, // lba_low
0, // lba_high
0, // count
status); // output: result status
end else begin
DEVICE_TITLE = "Expected Identify or DMA Write, got else";
......
tb_ahci_01.sav
View file @ f1b706b5
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Jan 30 05:58:18 2016
[*] Sat Jan 30 22:04:10 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160129225537152.fst"
[dumpfile_mtime] "Sat Jan 30 05:56:36 2016"
[dumpfile_size] 6775327
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160130143828459.fst"
[dumpfile_mtime] "Sat Jan 30 21:39:10 2016"
[dumpfile_size] 5291308
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 11870000
[timestart] 0
[size] 1823 1173
[pos] 1997 0
*-21.988060 24417034 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-23.533632 19124230 35135962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -759,7 +759,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@1401200
-axi_ahci_regs
@c00200
@800200
-ahci_fsm
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
......@@ -798,12 +798,14 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_last_act_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.cond_met_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pre_jump_w
@22
[color] 2
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_jump_addr[9:0]
@800028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
[color] 2
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_jump[2:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w
@1001200
......@@ -980,7 +982,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200
@1000200
-ahci_fsm
@c00200
-ahci_fis_receive
......@@ -2420,7 +2422,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_type_out[1:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_frame_busy
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_h2d_data_in[31:0]
@28
......@@ -2433,7 +2434,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_strobe_out
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_txing
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_in
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_last_out
@c00022
@800022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
......@@ -2448,11 +2449,13 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@29
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@28
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1401200
@1001200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair_0
......@@ -2491,7 +2494,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.data_busy_in
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_out[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_out[3:0]
@800022
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
......@@ -2510,9 +2513,22 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@1001200
@1401200
-group_end
@800200
-DEBUG_LAYERS
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_pending
@200
-
@1000200
-DEBUG_LAYERS
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
@800200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
......@@ -2541,7 +2557,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1000200
-states
-link
@800200
@c00200
-phy
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.comreset_send
......@@ -2587,7 +2603,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_charisk_out[3:0]
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
@1000200
@1401200
-phy
@c00200
-oob_ctrl
......@@ -2631,13 +2647,13 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
-device
@820
tb_ahci.dev.linkMonitorFIS.rprim[111:0]
@821
tb_ahci.dev.linkSendPrim.type[111:0]
@22
tb_ahci.dev.linkMonitorFIS.scrambler_value[31:0]
@200
-
@22
tb_ahci.dev.linkMonitorFIS.cnt
tb_ahci.dev.receive_id
tb_ahci.dev.receive_lock
tb_ahci.dev.receive_status
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment