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Commit e94b62c6 authored by Andrey Filippov's avatar Andrey Filippov
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added modupe to abort/recover AXI HP port after SATA errors, more debugging of the hardware

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.project
View file @ e94b62c6
......@@ -52,87 +52,87 @@
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ahci/ahci_dma.v
View file @ e94b62c6
......@@ -47,7 +47,8 @@ module ahci_dma (
input dev_wr, // write to device (valid at start)
input cmd_start, // start processing command table, reset prdbc
input prd_start, // at or after cmd_start - enable reading PRD/data (if any)
input cmd_abort, // try to abort a command TODO: Implement
input cmd_abort, // try to abort a command: Will keep afi_rready on until RD FIFO is empty and
// afi_awvalid (slowly one by one?) until afi_wacount is empty, keeping afi_wlast on
// Optional control of the AXI cache mode, default will be set to 4'h3, 4'h3 at mrst
input [3:0] axi_wr_cache_mode,
......@@ -70,6 +71,9 @@ module ahci_dma (
output reg prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
output reg cmd_busy, // all commands
output cmd_done, // @ mclk
output abort_busy,
output abort_done,
output axi_mismatch, // axi hp counters where empty when calculated counters were not (handled, but seems to be a bug - catch it)
// Data System memory -> HBA interface @ mclk
output [31:0] sys_out, // 32-bit data from the system memory to HBA (dma data)
......@@ -137,7 +141,11 @@ module ahci_dma (
// PL extra (non-AXI) signals
input [ 7:0] afi_rcount,
input [ 2:0] afi_racount,
output afi_rdissuecap1en
output afi_rdissuecap1en,
output [31:0] debug_out,
output [31:0] debug_out1
);
......@@ -180,7 +188,8 @@ module ahci_dma (
reg [21:1] wcount; // Word count
reg wcount_set;
reg [22:1] qwcount; // only [21:3] are used ([22] - carry from subtraction )
reg qwcount_done;
reg [21:3] qw_datawr_left;
reg [ 3:0] qw_datawr_burst;
reg qw_datawr_last;
......@@ -244,6 +253,33 @@ module ahci_dma (
wire fifo_nempty_mclk;
reg en_extra_din_r;
reg [31:0] ct_data_reg;
// reg abort_busy_hclk;
reg hrst_r;
wire abort_or_reset = cmd_abort_hclk || (hrst_r && !hrst);
// reg axi_dirty_r; // afi_wacount of afi_rcount are non-zero (assuming afi_wcount should be zero as addresses are posted first
wire afi_dirty;
reg afi_dirty_mclk;
wire abort_done_hclk;
wire abort_done_mclk;
reg abort_done_unneeded;
wire aborting;
wire afi_wvalid_data;
wire afi_wvalid_abort;
wire [5:0] afi_wid_abort;
wire afi_rready_abort;
wire afi_wlast_abort;
// wire abort_done;
reg abort_rq_mclk;
reg abort_busy_mclk;
wire [21:0] abort_debug;
assign afi_wvalid = aborting ? afi_wvalid_abort: afi_wvalid_data;
assign afi_wid = aborting ? afi_wid_abort: afi_id;
assign afi_rready = aborting ? afi_rready_abort : (afi_rd_ctl[0] || data_afi_re);
assign afi_wlast = aborting ? afi_wlast_abort: qw_datawr_last;
assign abort_done = abort_done_mclk || abort_done_unneeded;
assign abort_busy = abort_busy_mclk;
// assign prd_done = done_dev_wr || done_dev_rd;
......@@ -262,12 +298,12 @@ module ahci_dma (
assign afi_awlen = afi_alen;
assign afi_arvalid = axi_set_raddr_r;
assign afi_awvalid = axi_set_waddr_r;
assign afi_rready = afi_rd_ctl[0] || data_afi_re;
/// assign afi_rready = afi_rd_ctl[0] || data_afi_re;
assign afi_wstrb = {{2{afi_wstb4[3]}},{2{afi_wstb4[2]}},{2{afi_wstb4[1]}},{2{afi_wstb4[0]}}};
assign afi_wlast = qw_datawr_last;
/// assign afi_wlast = qw_datawr_last;
assign afi_awid = afi_id;
assign afi_wid = afi_id;
// assign afi_wid = afi_id;
assign afi_arid = afi_id;
// Unused or static output signals
......@@ -290,6 +326,16 @@ module ahci_dma (
assign extra_din = en_extra_din_r && fifo_nempty_mclk;
// reg [31:0] ct_data_reg;
always @ (posedge mclk) begin
if (mrst) afi_dirty_mclk <= 0;
afi_dirty_mclk <=afi_dirty;
abort_rq_mclk <= cmd_abort && afi_dirty_mclk;
abort_done_unneeded <= cmd_abort && !afi_dirty_mclk;
if (mrst || abort_done) abort_busy_mclk <= 0;
else if (cmd_abort) abort_busy_mclk <= 1;
if (ct_re[0]) ct_data_reg <= ct_data_ram[ct_addr];
if (ct_re[1]) ct_data <= ct_data_reg;
......@@ -332,12 +378,19 @@ module ahci_dma (
wire [21:1] wcount_plus_data_addr = wcount[21:1] + data_addr[2:1];
always @ (posedge hclk) begin
hrst_r <= hrst;
// axi_dirty_r <= (|afi_wacount) || (|afi_rcount); // afi_wacount of afi_rcount are non-zero (assuming afi_wcount should be zero as addresses are posted first
// if (abort_or_reset && axi_dirty_r) abort_busy_hclk <= 1'b1;
addr_data_rq_r <= addr_data_rq_w;
prd_start_hclk_r <= prd_start_hclk;
if (hrst || cmd_abort_hclk) prd_enabled <= 0;
else if (prd_start_hclk_r) prd_enabled <= 1; // presedence over cmd_start_hclk
if (hrst || abort_or_reset) prd_enabled <= 0;
else if (prd_start_hclk_r) prd_enabled <= 1; // precedence over cmd_start_hclk
else if (cmd_start_hclk) prd_enabled <= 0;
......@@ -388,17 +441,21 @@ module ahci_dma (
/// if (addr_data_rq) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3]; // early calculate
if (addr_data_rq_r) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3]; // early calculate
/// if (wcount_set) qwcount[21:1] <= wcount[21:1] + data_addr[2:1]; //minus 1
/// else if (axi_set_addr_data_w) qwcount[21:7] <= qwcount[21:7] - 1; // may get negative
if (wcount_set) qwcount[22:1] <= {1'b0,wcount_plus_data_addr[21:1]}; // wcount[21:1] + data_addr[2:1]; //minus 1
if (wcount_set) qwcount[22:7] <= {1'b0,wcount_plus_data_addr[21:7]}; // wcount[21:1] + data_addr[2:1]; //minus 1
else if (axi_set_addr_data_w) qwcount[22:7] <= qwcount[22:7] - 1; // may get negative
if (wcount_set) qwcount[ 6:1] <= wcount_plus_data_addr[6:1]; // wcount[21:1] + data_addr[2:1]; //minus 1
if (wcount_set) qwcount_done <= 0;
else if (axi_set_addr_data_w && (qwcount[21:7]==0)) qwcount_done <= 1;
//wcount_plus_data_addr
/// data_next_burst <= axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid
/// data_next_burst <= !qwcount[22] && axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid
data_next_burst <= !qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
/// data_next_burst <= !qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
data_next_burst <= !qwcount_done && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid
// Get PRD data
// store data address from PRD, increment when needed
......@@ -447,18 +504,15 @@ module ahci_dma (
// calculate afi_wlast - it is (qw_datawr_burst == 0), just use register qw_datawr_last
if (prd_wr) qw_datawr_last <= qwcount[21:3] == 0;
/// else if (afi_wvalid) qw_datawr_last <= qw_datawr_burst == 1;
else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && (qw_datawr_left[21:3] == 16)); // last case - n*16 + 1 (last burst single)
if (prd_wr) qw_datawr_last <= (qwcount[21:3] == 0);
else if (afi_wvalid_data) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && (qw_datawr_left[21:3] == 16)); // last case - n*16 + 1 (last burst single)
if (prd_wr) qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3];
/// else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf
/// else if (afi_wvalid && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf
else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 1)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf
else if (afi_wvalid) qw_datawr_burst <= qw_datawr_burst - 1;
if (prd_wr) qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3];
else if (afi_wvalid_data && qw_datawr_last && (qw_datawr_left[21:7] == 1)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf
else if (afi_wvalid_data) qw_datawr_burst <= qw_datawr_burst - 1;
if (prd_wr) qw_datawr_left[21:3] <= qwcount[21:3];
else if (afi_wvalid && qw_datawr_last) qw_datawr_left[21:7] <= qw_datawr_left[21:7] - 1; // can go negative - OK?
if (prd_wr) qw_datawr_left[21:3] <= qwcount[21:3];
else if (afi_wvalid_data && qw_datawr_last) qw_datawr_left[21:7] <= qw_datawr_left[21:7] - 1; // can go negative - OK?
// Count AXI IDs
if (hrst) ct_id <= 0;
......@@ -475,6 +529,44 @@ module ahci_dma (
end
// Flushing AXI HP - there is no easy way to reset it, so if there was an error in SATA communication we need to read any data
// that was already requested (over AXI read adderss channel) and send junk data (with appropriate afi_wlast bit) to the write
// channel. THis module is not reset and even bitsteram relaod will not work, so hrst input is used just as disable paying attention
// to other inputs, doe s not reset anything inside.
// FPGA should not be reset /reloaded if there are any outstanding transactions not aborted
// Current implementation counts all transactions and relies on it - not on afi_*count. TODO: Implement recovering from mismatch
axi_hp_abort axi_hp_abort_i (
.hclk (hclk), // input
.hrst (hrst), // input
.abort (abort_or_reset), // input
.busy (aborting), // output
.done (abort_done_hclk), // output reg
.afi_awvalid (afi_awvalid), // input
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // input[5:0]
.afi_awlen (afi_awlen), // input[3:0]
.afi_wvalid_in (afi_wvalid), // input
.afi_wready (afi_wready), // input
.afi_wvalid (afi_wvalid_abort), // output
.afi_wid (afi_wid_abort), // output[5:0] reg
.afi_arvalid (afi_arvalid), // input
.afi_arready (afi_arready), // input
.afi_arlen (afi_arlen), // input[3:0]
.afi_rready_in (afi_rready), // input
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready_abort), // output
.afi_wlast (afi_wlast_abort), // output
.afi_racount (afi_racount), // input[2:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wcount (afi_wcount), // input[7:0]
.dirty (afi_dirty), // output reg
.axi_mismatch (axi_mismatch), // output_reg
.debug (abort_debug) // output[21:0]
);
ahci_dma_rd_fifo #( // memory to device
.WCNT_BITS (21),
......@@ -516,7 +608,7 @@ module ahci_dma (
// .dout_av (), // input
.dout_av_many (afi_wcount_many),// input
.last_prd (last_prd), // input
.dout_we (afi_wvalid), // output
.dout_we (afi_wvalid_data),// output
.dout_wstb (afi_wstb4), // output[3:0] reg
.done (done_dev_rd), // output reg
.busy (), // output
......@@ -544,8 +636,8 @@ module ahci_dma (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (hclk), // input
.in_pulse (cmd_abort), // input
.out_pulse (cmd_abort_hclk), // output
.in_pulse (abort_rq_mclk), // input
.out_pulse (cmd_abort_hclk), // output
.busy() // output
);
pulse_cross_clock #(
......@@ -595,8 +687,99 @@ module ahci_dma (
.busy() // output
);
pulse_cross_clock #(
.EXTRA_DLY(0)
) abort_done_i (
.rst (hrst), // input
.src_clk (hclk), // input
.dst_clk (mclk), // input
.in_pulse (abort_done_hclk), // input
.out_pulse (abort_done_mclk), // output
.busy() // output
);
//abort_done_hclk
reg [7:0] dbg_afi_awvalid_cntr;
reg [7:0] dbg_qwcount;
reg [7:0] dbg_qwcount_cntr;
reg [7:0] dbg_set_raddr_count;
reg [7:0] dbg_set_waddr_count;
reg dbg_was_mismatch;
// if (axi_set_raddr_w || axi_set_waddr_w) begin
//data_next_burst
always @ (posedge hclk) begin
if (hrst) dbg_afi_awvalid_cntr <= 0;
else if (axi_set_waddr_r) dbg_afi_awvalid_cntr <= dbg_afi_awvalid_cntr + 1;
// if (hrst) dbg_last_afi_len <= 0;
if (axi_set_raddr_w || axi_set_waddr_w) begin
end
if (wcount_set) dbg_qwcount <= wcount_plus_data_addr[14:7];
// if (wcount_set) qwcount[22:7] <= {1'b0,wcount_plus_data_addr[21:7]}; // wcount[21:1] + data_addr[2:1]; //minus 1
if (hrst) dbg_qwcount_cntr <= 0;
// else if (wcount_set) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
// else if (data_next_burst) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
else if (!qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7])) dbg_qwcount_cntr <= dbg_qwcount_cntr + 1;
if (hrst) dbg_set_raddr_count <= 0;
// else if (axi_set_raddr_w) dbg_set_raddr_count <= dbg_set_raddr_count + 1;
else if (axi_set_raddr_ready && raddr_data_pend) dbg_set_raddr_count <= dbg_set_raddr_count + 1;
if (hrst) dbg_set_waddr_count <= 0;
// else if (axi_set_waddr_w) dbg_set_waddr_count <= dbg_set_waddr_count + 1;
// else if (axi_set_waddr_ready && waddr_data_pend) dbg_set_waddr_count <= dbg_set_waddr_count + 1; //0x14
else if (addr_data_rq_w) dbg_set_waddr_count <= dbg_set_waddr_count + 1; //0x14
if (hrst) dbg_was_mismatch <= 0;
else if (axi_mismatch) dbg_was_mismatch <= 1;
end
assign debug_out = {int_data_addr [3:0],
qwcount_done, // prd_rd_busy,
afi_racount [2:0],
//--
afi_rcount [7:0],
//--
ct_busy,
cmd_busy,
afi_wacount [5:0],
//--
afi_wcount [7:0]};
/*
assign debug_out = {
qwcount[22:7],
dev_rd_id,
dev_wr_id,
prd_id,
ct_id
};
assign debug_out = {qwcount_done,
2'b0,
dev_wr_id,
prd_id,
wcount[21:1]
};
assign debug_out1 = { //dbg_set_raddr_count[7:0],
qwcount_done,
afi_rcount[6:0],
//{qwcount[22], qwcount[13:7]},
dbg_set_waddr_count[7:0],
dbg_qwcount[3:0],
afi_alen[3:0],
dbg_qwcount_cntr[7:0]};
*/
assign debug_out1 = { //dbg_set_raddr_count[7:0]
8'b0 ,
dbg_was_mismatch,
1'b0,
abort_debug[21:0]}; // {aw_count[5:0], w_count[7:0], r_count[7:0]};
//
endmodule
ahci/ahci_fsm.v
View file @ e94b62c6
......@@ -144,7 +144,7 @@ module ahci_fsm
input dma_cmd_busy, // output reg (DMA engine is processing PRDs)
/// input dma_cmd_done, // output (last PRD is over)
output dma_cmd_abort, // try to abort a command
input dma_abort_done, // if abort is not needed, will generate dma_abort_done just next cycle
// Communication with ahci_fis_receive (some are unused)
// Debug features
......@@ -257,15 +257,20 @@ module ahci_fsm
// reg jump_r;
reg [2:0] fsm_jump;
wire fsm_next;
reg fsm_next_r;
// reg fsm_next_r;
reg fsm_actions; // processing actions
reg fsm_act_busy;
reg [1:0] fsm_transitions; // processing transitions
reg fsm_preload; // read first sequence data (2 cycles for regen)
// wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions
// reg [7:0] conditions;
wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);
wire fsm_act_done = get_fis_done || xmit_done || (syncesc_send_pend && syncesc_send_done);
// wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);
wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);
wire fsm_act_done = get_fis_done ||
xmit_done ||
(syncesc_send_pend && syncesc_send_done) ||
dma_abort_done ||
asynq_rq; // cominit_got || pcmd_st_cleared
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17];
......@@ -283,6 +288,14 @@ module ahci_fsm
wire phy_ready_chng_w = !hba_rst && !was_rst && (phy_ready != phy_ready_prev);
reg was_last_action_r; // delay last action if it was fsm_wait_act;
wire fsm_transitions_w = // next will be transitions processing
(fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
(fsm_act_busy && fsm_act_done && was_last_action_r);
wire conditions_ce = // copy all conditions to the register so they will not change while iterating through them
!fsm_transitions_w && !fsm_transitions[0];
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
......@@ -344,8 +357,9 @@ module ahci_fsm
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0;
else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
(fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
else fsm_transitions <= {fsm_transitions[0],fsm_transitions[0]};
if (hba_rst) fsm_preload <= 0;
......@@ -460,6 +474,7 @@ module ahci_fsm
// Condition inputs may be registered if needed
condition_mux condition_mux_i (
.clk (mclk), // input
.ce (conditions_ce), // input
.sel (pgm_data[17:10]), // input[7:0]
.condition (cond_met_w), // output
//COMPOSITE
......
ahci/ahci_sata_layers.v
View file @ e94b62c6
......@@ -92,7 +92,9 @@ module ahci_sata_layers #(
input wire rxp_in,
input wire rxn_in,
output [31:0] debug_sata
output [31:0] debug_phy,
output [31:0] debug_link
);
localparam PHY_SPEED = 2; // SATA2
......@@ -169,8 +171,8 @@ module ahci_sata_layers #(
wire d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO
reg h2d_pending; // HBA started sending FIS to fifo
wire [31:0] debug_phy;
wire [31:0] debug_link;
// wire [31:0] debug_phy;
// wire [31:0] debug_link;
wire rxelsfull;
wire rxelsempty;
......@@ -184,7 +186,7 @@ module ahci_sata_layers #(
// assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; //
// assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //
assign debug_sata = {debug_link[27:20],debug_phy[23:0]} ; //
// assign debug_sata = {debug_link[27:20],debug_phy[23:0]} ; //
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty;
......@@ -260,7 +262,7 @@ module ahci_sata_layers #(
.link_reset (ll_link_reset), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current recieving session
.link_established (link_established),
// inputs from phy
.phy_ready (phy_ready), // input wire // phy is ready - link is established
......
ahci/ahci_top.v
View file @ e94b62c6
......@@ -183,7 +183,8 @@ module ahci_top#(
output irq, // CPU interrupt request
input [31:0] debug_in
input [31:0] debug_in_phy,
input [31:0] debug_in_link
);
......@@ -265,6 +266,11 @@ module ahci_top#(
wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
wire dma_cmd_busy; // output reg (DMA engine is processing PRDs)
wire dma_cmd_done; // output (last PRD is over)
wire dma_abort_busy;
wire dma_abort_done;
wire axi_mismatch;
wire [31:0] dma_dout; // output[31:0]
wire dma_dav; // output
wire dma_re; // input
......@@ -448,6 +454,8 @@ module ahci_top#(
wire pxci0; // pxCI current value
wire [9:0] last_jump_addr;
wire [31:0] debug_dma;
wire [31:0] debug_dma1;
// Async FF
always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0;
......@@ -561,81 +569,79 @@ module ahci_top#(
.dma_cmd_busy (dma_cmd_busy), // input
/// .dma_cmd_done (dma_cmd_done), // input
.dma_cmd_abort (dma_cmd_abort_fsm), // output
.dma_abort_done (dma_abort_done), // input
.fis_first_invalid (frcv_first_invalid),// input
.fis_first_flush (frcv_first_flush), // output
.fis_first_invalid (frcv_first_invalid),// input
.fis_first_flush (frcv_first_flush), // output
.fis_first_vld (frcv_first_vld), // input
.fis_type (d2h_data[7:0]), // input[7:0] FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
.bist_bits (d2h_data[23:16]), // bits that define built-in self test
.fis_first_vld (frcv_first_vld), // input
.fis_type (d2h_data[7:0]), // input[7:0] FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
.bist_bits (d2h_data[23:16]), // bits that define built-in self test
.get_dsfis (frcv_get_dsfis), // output
.get_psfis (frcv_get_psfis), // output
.get_rfis (frcv_get_rfis), // output
.get_sdbfis (frcv_get_sdbfis), // output
.get_ufis (frcv_get_ufis), // output
.get_data_fis (frcv_get_data_fis), // output
.get_ignore (frcv_get_ignore), // output
/// .get_fis_busy (frcv_busy), // input
.get_fis_done (frcv_done), // input
.fis_ok (frcv_ok), // input
.fis_err (frcv_err), // input
.fis_ferr (frcv_ferr), // input
.fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
.get_dsfis (frcv_get_dsfis), // output
.get_psfis (frcv_get_psfis), // output
.get_rfis (frcv_get_rfis), // output
.get_sdbfis (frcv_get_sdbfis), // output
.get_ufis (frcv_get_ufis), // output
.get_data_fis (frcv_get_data_fis), // output
.get_ignore (frcv_get_ignore), // output
/// .get_fis_busy (frcv_busy), // input
.get_fis_done (frcv_done), // input
.fis_ok (frcv_ok), // input
.fis_err (frcv_err), // input
.fis_ferr (frcv_ferr), // input
.fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
.set_update_sig (frcv_set_update_sig),// output
/// .pUpdateSig (frcv_pUpdateSig), // input
/// .sig_available (frcv_sig_available), // input
.update_sig (frcv_update_sig), // output
.set_update_sig (frcv_set_update_sig),// output
/// .pUpdateSig (frcv_pUpdateSig), // input
/// .sig_available (frcv_sig_available), // input
.update_sig (frcv_update_sig), // output
.update_err_sts (frcv_update_err_sts),// output
.update_pio (frcv_update_pio), // output
.update_prdbc (frcv_update_prdbc), // output
.clear_bsy_drq (frcv_clear_bsy_drq), // output
.clear_bsy_set_drq(frcv_clear_bsy_set_drq), //output
.set_bsy (frcv_set_bsy), // output
.set_sts_7f (frcv_set_sts_7f), // output
.set_sts_80 (frcv_set_sts_80), // output
.clear_xfer_cntr (frcv_clear_xfer_cntr), //output Clear pXferCntr
.decr_dwcr (frcv_decr_dwcr), // output increment pXferCntr after transmit by data transmitted)
.decr_dwcw (frcv_decr_dwcw), // output increment pXferCntr after transmit by data transmitted)
.update_err_sts (frcv_update_err_sts),// output
.update_pio (frcv_update_pio), // output
.update_prdbc (frcv_update_prdbc), // output
.clear_bsy_drq (frcv_clear_bsy_drq), // output
.clear_bsy_set_drq (frcv_clear_bsy_set_drq), //output
.set_bsy (frcv_set_bsy), // output
.set_sts_7f (frcv_set_sts_7f), // output
.set_sts_80 (frcv_set_sts_80), // output
.clear_xfer_cntr (frcv_clear_xfer_cntr), //output Clear pXferCntr
.decr_dwcr (frcv_decr_dwcr), // output increment pXferCntr after transmit by data transmitted)
.decr_dwcw (frcv_decr_dwcw), // output increment pXferCntr after transmit by data transmitted)
// .decr_DXC_dw (data_out_dwords), // output[11:2] **** Probably not needed
.pxcmd_fre (pcmd_fre), // input
.pPioXfer (pPioXfer), // input
.tfd_sts (tfd_sts), // input[7:0]
/// .tfd_err (tfd_err), // input[7:0]
.fis_i (fis_i), // input
.pxcmd_fre (pcmd_fre), // input
.pPioXfer (pPioXfer), // input
.tfd_sts (tfd_sts), // input[7:0]
/// .tfd_err (tfd_err), // input[7:0]
.fis_i (fis_i), // input
/// .sdb_n (sdb_n), // input
.dma_a (dma_a), // input
.dma_a (dma_a), // input
/// .dma_d (dma_d), // input
.pio_i (pio_i), // input
.pio_d (pio_d), // input
.pio_i (pio_i), // input
.pio_d (pio_d), // input
/// .sactive0 (sactive0), // input
/// .pio_es (pio_es), // input[7:0]
/// .xfer_cntr (xfer_cntr[31:2]), // input[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // input
.xfer_cntr_zero (xfer_cntr_zero), // input
.fetch_cmd (fsnd_fetch_cmd), // output
.cfis_xmit (fsnd_cfis_xmit), // output
.dx_xmit (fsnd_dx_xmit), // output
.atapi_xmit (fsnd_atapi_xmit), // output
.xmit_done (fsnd_done), // input
.fetch_cmd (fsnd_fetch_cmd), // output
.cfis_xmit (fsnd_cfis_xmit), // output
.dx_xmit (fsnd_dx_xmit), // output
.atapi_xmit (fsnd_atapi_xmit), // output
.xmit_done (fsnd_done), // input
/// .xmit_busy (fsnd_busy), // input
.clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS
.pCmdToIssue (fsnd_pCmdToIssue), // input
.dx_err (fsnd_dx_err), // input[1:0]
.clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS
.pCmdToIssue (fsnd_pCmdToIssue), // input
.dx_err (fsnd_dx_err), // input[1:0]
/// .ch_prdtl (prdtl), // input[15:0]
.ch_c (fsnd_ch_c), // input
.ch_b (fsnd_ch_b), // input
.ch_r (fsnd_ch_r), // input
.ch_p (fsnd_ch_p), // input
.ch_w (fsnd_ch_w), // input
.ch_a (fsnd_ch_a), // input
.ch_c (fsnd_ch_c), // input
.ch_b (fsnd_ch_b), // input
.ch_r (fsnd_ch_r), // input
.ch_p (fsnd_ch_p), // input
.ch_w (fsnd_ch_w), // input
.ch_a (fsnd_ch_a), // input
/// .ch_cfl (fsnd_ch_cfl), // input[4:0]
/// .dwords_sent (data_out_dwords) // input[11:0] ????
.last_jump_addr (last_jump_addr)
.last_jump_addr (last_jump_addr)
);
......@@ -697,8 +703,11 @@ module ahci_top#(
.afi_rcache (axi_rd_cache_mode),// output[3:0] reg
.afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output
.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
.was_port_rst (was_port_rst), // output
.debug_in0 (debug_dma), // input[31:0]
.debug_in1 (debug_dma1), // debug_in_link), // input[31:0]
.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
.debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // input
.datascope_waddr (datascope_waddr), // input[9:0]
......@@ -823,6 +832,9 @@ module ahci_top#(
.cmd_busy (dma_cmd_busy), // dma_cmd_busy), // output reg Some data to transmit!
.cmd_done (dma_cmd_done), // output
.abort_busy (dma_abort_busy),
.abort_done (dma_abort_done),
.axi_mismatch (axi_mismatch), // handled, but may report as an error - axi counters are 0, but calculated ones are not
.sys_out (dma_dout), // output[31:0]
.sys_dav (dma_dav), // output
.sys_re (dma_re), // input
......@@ -874,7 +886,9 @@ module ahci_top#(
.afi_rresp (afi_rresp), // input[1:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en) // output
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.debug_out (debug_dma), // output[31:0]
.debug_out1 (debug_dma1) // output[31:0]
);
ahci_fis_receive #(
......@@ -1023,15 +1037,31 @@ wire [9:0] xmit_dbg_01;
localparam DATASCOPE_CFIS_START=0;
reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run;
reg [8:0] datascope_cntr;
reg datascope_was_busy;
/// reg [8:0] datascope_cntr;
/// reg datascope_was_busy;
assign datascope_clk = mclk;
// assign datascope_di = datascope_run[0]? {h2d_type, dma_dav, datascope_was_busy, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
assign datascope_di = datascope_run[0]? {h2d_type, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2);
assign datascope_waddr = datascope_waddr_r;
// assign datascope_di = datascope_run[0]? {h2d_type, dma_dav, datascope_was_busy, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
/// assign datascope_di = datascope_run[0]? {h2d_type, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
always @(posedge mclk) begin
// Datascope provides just outgoing data, followed by the dword counter with 16'hffff in the high word
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2);
// assign datascope_di = datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r};
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2) || d2h_ready;
assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {16'hffff,{16-ADDRESS_BITS{1'b0}},datascope_waddr_r});
/// assign datascope_we = |datascope_run;
/*
assign datascope_di = datascope_run[0]? {h2d_type, // 2 bits
dma_ct_re[0], // 1 bit
dma_ct_addr[4:0], // 5 bits
//------
dma_ct_data[7:0], //8 bits (lower)
datascope_cntr[3:0], // 4 bits
h2d_data[11:0]} : // 12 bits
{{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
*/ always @(posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
......@@ -1041,12 +1071,17 @@ wire [9:0] xmit_dbg_01;
if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
if (fsnd_cfis_xmit) datascope_cntr <= 0;
else datascope_cntr <= datascope_cntr + 1;
/// if (fsnd_cfis_xmit) datascope_cntr <= 0;
/// else datascope_cntr <= datascope_cntr + 1;
if (fsnd_cfis_xmit) datascope_was_busy <= ahci_fis_transmit_busy;
/// if (fsnd_cfis_xmit) datascope_was_busy <= ahci_fis_transmit_busy;
end
/*
.ct_addr (dma_ct_addr), // output[4:0] reg
.ct_re (dma_ct_re), // output[1:0]
.ct_data (dma_ct_data), // input[31:0]
*/
`endif
......
ahci/axi_ahci_regs.v
View file @ e94b62c6
......@@ -115,7 +115,10 @@ module axi_ahci_regs#(
output afi_cache_set,
output was_hba_rst, // last reset was hba reset (not counting system reset)
output was_port_rst, // last reset was port reset
input [31:0] debug_in
input [31:0] debug_in0,
input [31:0] debug_in1,
input [31:0] debug_in2,
input [31:0] debug_in3
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
,input datascope_clk,
......@@ -188,6 +191,7 @@ module axi_ahci_regs#(
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
reg debug_rd_r;
reg [31:0] debug_r;
assign bram_addr = bram_ren[0] ? bram_raddr[ADDRESS_BITS-1:0] : (bram_wen_r ? bram_waddr_r : bram_waddr[ADDRESS_BITS-1:0]);
......@@ -198,7 +202,6 @@ module axi_ahci_regs#(
assign was_hba_rst = was_hba_rst_r[0];
assign was_port_rst = was_port_rst_r[0];
always @(posedge aclk) begin
if (arst) write_busy_r <= 0;
......@@ -207,7 +210,7 @@ module axi_ahci_regs#(
if (bram_wen) bram_wdata_r <= bram_wdata;
if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_in : bram_rdata;
// if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_in : bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
......@@ -215,8 +218,17 @@ module axi_ahci_regs#(
if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs (With AXIBRAM_BITS will be duplicated)
if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2):
(bram_raddr[0] ? debug_in1: debug_in0);
if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_r : bram_rdata;
end
//debug_rd_r
generate
genvar i;
for (i=0; i < 32; i=i+1) begin: bit_type_block
......@@ -281,10 +293,6 @@ module axi_ahci_regs#(
if (pgm_fsm_set_w) pgm_ad <= ahci_regs_di[17:0];
end
always @(posedge aclk) begin
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs (With AXIBRAM_BITS will be duplicated)
end
//debug_rd_r
/*
......
ahci/axi_hp_abort.v 0 → 100644
View file @ e94b62c6
/*******************************************************************************
* Module: axi_hp_abort
* Date:2016-02-07
* Author: andrey
* Description: Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
* Reset only by global reset (system POR) - probably it is not possible to just
* reset PL or relaod bitfile,
*
* Copyright (c) 2016 Elphel, Inc .
* axi_hp_abort.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axi_hp_abort.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module axi_hp_abort(
input hclk,
input hrst, // just disables processing inputs
input abort,
output busy, // should disable control of afi_wvalid, afi_awid
output reg done,
input afi_awvalid, // afi_awready is supposed to be always on when afi_awvalid (caller uses fifo counetrs) ?
input afi_awready, //
input [ 5:0] afi_awid,
input [3:0] afi_awlen,
input afi_wvalid_in,
input afi_wready,
output afi_wvalid,
output reg [ 5:0] afi_wid,
input afi_arvalid,
input afi_arready,
input [ 3:0] afi_arlen,
input afi_rready_in,
input afi_rvalid,
output afi_rready,
output afi_wlast,
// TODO: Try to resolve problems when afi_racount, afi_wacount afi_wcount do not match expected
input [ 2:0] afi_racount,
input [ 7:0] afi_rcount,
input [ 5:0] afi_wacount,
input [ 7:0] afi_wcount,
output reg dirty, // single bit to be sampled in different clock domain to see if flushing is needed
output reg axi_mismatch, // calculated as 'dirty' but axi hp counters are 0
output [21:0] debug
);
reg busy_r;
wire done_w = busy_r && !dirty ;
reg [3:0] aw_lengths_ram[0:31];
reg [4:0] aw_lengths_waddr = 0;
reg [4:0] aw_lengths_raddr = 0;
reg [5:0] aw_count = 0;
reg [7:0] w_count = 0;
reg [7:0] r_count = 0;
reg adav = 0;
wire arwr = !hrst && afi_arvalid && afi_arready;
wire drd = !hrst && afi_rvalid && afi_rready_in;
wire awr = !hrst && afi_awvalid && afi_awready;
reg ard_r = 0; // additional length read if not much data
wire ard = adav && ((|w_count[7:4]) || ard_r);
wire wwr = !hrst && afi_wready && afi_wvalid_in;
reg afi_rready_r;
reg afi_wlast_r; // wait one cycle after last in each burst (just to ease timing)
reg busy_aborting; // actually aborting
wire reset_counters = busy_r && !busy_aborting;
assign busy = busy_r;
assign afi_rready = busy_aborting && (|r_count) && ((|afi_rcount[7:1]) || (!afi_rready_r && afi_rcount[0]));
assign afi_wlast = busy_aborting && adav && (w_count[3:0] == aw_lengths_ram[aw_lengths_raddr]);
assign afi_wvalid = busy_aborting && adav && !afi_wlast_r;
assign debug = {aw_count[5:0], w_count[7:0], r_count[7:0]};
// Watch for transactios performed by others (and this one too)
always @ (posedge hclk) begin
// read channel
if (reset_counters) r_count <= 0;
else if (drd)
if (arwr) r_count <= r_count + {4'b0, afi_arlen};
else r_count <= r_count - 1;
else
if (arwr) r_count <= w_count + {4'b0, afi_arlen} + 1;
// write channel
if (awr) afi_wid <= afi_awid; // one command is supposed to use just one awid/wid
if (awr) aw_lengths_ram [aw_lengths_waddr] <= afi_awlen;
if (reset_counters) aw_lengths_waddr <= 0;
else if (awr) aw_lengths_waddr <= aw_lengths_waddr + 1;
if (reset_counters) aw_lengths_raddr <= 0;
else if (ard) aw_lengths_raddr <= aw_lengths_raddr + 1;
if (reset_counters) aw_count <= 0;
else if ( awr && !ard) aw_count <= aw_count + 1;
else if (!awr && ard) aw_count <= aw_count - 1;
adav <= !reset_counters && (|aw_count[5:1]) || ((awr || aw_count[0]) && !ard) || (awr && aw_count[0]);
ard_r <= !ard && adav && (w_count[3:0] > aw_lengths_ram[aw_lengths_raddr]);
if (reset_counters) w_count <= 0;
else if (wwr)
if (ard) w_count <= w_count - {4'b0, aw_lengths_ram[aw_lengths_raddr]};
else w_count <= w_count + 1;
else
if (ard) w_count <= w_count - {4'b0, aw_lengths_ram[aw_lengths_raddr]} - 1;
dirty <= (|r_count) || (|aw_count); // assuming w_count can never be non-zero? - no
end
// flushing part
always @ (posedge hclk) begin
if (abort) busy_r <= 1;
else if (done_w) busy_r <= 0;
if (abort && ((|afi_racount) || (|afi_rcount) || (|afi_wacount) || (|afi_wcount))) busy_aborting <= 1;
else if (done_w) busy_aborting <= 0;
done <= done_w;
afi_rready_r <= afi_rready;
afi_wlast_r <= afi_wlast;
axi_mismatch <= busy && !busy_aborting && dirty; //
end
endmodule
ahci/sata_ahci_top.v
View file @ e94b62c6
......@@ -224,7 +224,8 @@
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
wire [31:0] debug_sata;
wire [31:0] debug_phy;
wire [31:0] debug_link;
always @ (posedge hclk or posedge arst) begin
if (arst) nhrst_r <= 0;
......@@ -365,7 +366,8 @@
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output
.debug_in (debug_sata) // input[31:0]
.debug_in_phy (debug_phy), // input[31:0]
.debug_in_link (debug_link) // input[31:0]
);
ahci_sata_layers #(
......@@ -424,7 +426,8 @@
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire
.debug_sata (debug_sata) // output[31:0]
.debug_phy (debug_phy), // output[31:0]
.debug_link (debug_link) // output[31:0]
);
......
generated/action_decoder.v
View file @ e94b62c6
/*******************************************************************************
* Module: action_decoder
* Date:2016-01-27
* Date:2016-02-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
......
generated/condition_mux.v
View file @ e94b62c6
/*******************************************************************************
* Module: condition_mux
* Date:2016-01-27
* Date:2016-02-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
......@@ -9,6 +9,7 @@
module condition_mux (
input clk,
input ce, // enable recording all conditions
input [ 7:0] sel,
output condition,
input ST_NB_ND,
......@@ -57,57 +58,104 @@ module condition_mux (
input X_RDY_COLLISION);
wire [44:0] masked;
reg [43:0] registered;
reg [ 5:0] cond_r;
assign condition = |cond_r;
assign masked[ 0] = ST_NB_ND && sel[ 2] && sel[ 1] && sel[ 0];
assign masked[ 1] = PXCI0_NOT_CMDTOISSUE && sel[ 3] && sel[ 1] && sel[ 0];
assign masked[ 2] = PCTI_CTBAR_XCZ && sel[ 4] && sel[ 1] && sel[ 0];
assign masked[ 3] = PCTI_XCZ && sel[ 5] && sel[ 1] && sel[ 0];
assign masked[ 4] = NST_D2HR && sel[ 6] && sel[ 1] && sel[ 0];
assign masked[ 5] = NPD_NCA && sel[ 7] && sel[ 1] && sel[ 0];
assign masked[ 6] = CHW_DMAA && sel[ 3] && sel[ 2] && sel[ 0];
assign masked[ 7] = SCTL_DET_CHANGED_TO_4 && sel[ 4] && sel[ 2] && sel[ 0];
assign masked[ 8] = SCTL_DET_CHANGED_TO_1 && sel[ 5] && sel[ 2] && sel[ 0];
assign masked[ 9] = PXSSTS_DET_NE_3 && sel[ 6] && sel[ 2] && sel[ 0];
assign masked[10] = PXSSTS_DET_EQ_1 && sel[ 7] && sel[ 2] && sel[ 0];
assign masked[11] = NPCMD_FRE && sel[ 4] && sel[ 3] && sel[ 0];
assign masked[12] = FIS_OK && sel[ 5] && sel[ 3] && sel[ 0];
assign masked[13] = FIS_ERR && sel[ 6] && sel[ 3] && sel[ 0];
assign masked[14] = FIS_FERR && sel[ 7] && sel[ 3] && sel[ 0];
assign masked[15] = FIS_EXTRA && sel[ 5] && sel[ 4] && sel[ 0];
assign masked[16] = FIS_FIRST_INVALID && sel[ 6] && sel[ 4] && sel[ 0];
assign masked[17] = FR_D2HR && sel[ 7] && sel[ 4] && sel[ 0];
assign masked[18] = FIS_DATA && sel[ 6] && sel[ 5] && sel[ 0];
assign masked[19] = FIS_ANY && sel[ 7] && sel[ 5] && sel[ 0];
assign masked[20] = NB_ND_D2HR_PIO && sel[ 7] && sel[ 6] && sel[ 0];
assign masked[21] = D2HR && sel[ 3] && sel[ 2] && sel[ 1];
assign masked[22] = SDB && sel[ 4] && sel[ 2] && sel[ 1];
assign masked[23] = DMA_ACT && sel[ 5] && sel[ 2] && sel[ 1];
assign masked[24] = DMA_SETUP && sel[ 6] && sel[ 2] && sel[ 1];
assign masked[25] = BIST_ACT_FE && sel[ 7] && sel[ 2] && sel[ 1];
assign masked[26] = BIST_ACT && sel[ 4] && sel[ 3] && sel[ 1];
assign masked[27] = PIO_SETUP && sel[ 5] && sel[ 3] && sel[ 1];
assign masked[28] = NB_ND && sel[ 6] && sel[ 3] && sel[ 1];
assign masked[29] = TFD_STS_ERR && sel[ 7] && sel[ 3] && sel[ 1];
assign masked[30] = FIS_I && sel[ 5] && sel[ 4] && sel[ 1];
assign masked[31] = PIO_I && sel[ 6] && sel[ 4] && sel[ 1];
assign masked[32] = NPD && sel[ 7] && sel[ 4] && sel[ 1];
assign masked[33] = PIOX && sel[ 6] && sel[ 5] && sel[ 1];
assign masked[34] = XFER0 && sel[ 7] && sel[ 5] && sel[ 1];
assign masked[35] = PIOX_XFER0 && sel[ 7] && sel[ 6] && sel[ 1];
assign masked[36] = CTBAA_CTBAP && sel[ 4] && sel[ 3] && sel[ 2];
assign masked[37] = CTBAP && sel[ 5] && sel[ 3] && sel[ 2];
assign masked[38] = CTBA_B && sel[ 6] && sel[ 3] && sel[ 2];
assign masked[39] = CTBA_C && sel[ 7] && sel[ 3] && sel[ 2];
assign masked[40] = TX_ERR && sel[ 5] && sel[ 4] && sel[ 2];
assign masked[41] = SYNCESC_ERR && sel[ 6] && sel[ 4] && sel[ 2];
assign masked[42] = DMA_PRD_IRQ_PEND && sel[ 7] && sel[ 4] && sel[ 2];
assign masked[43] = X_RDY_COLLISION && sel[ 6] && sel[ 5] && sel[ 2];
assign masked[ 0] = registered[ 0] && sel[ 2] && sel[ 1] && sel[ 0];
assign masked[ 1] = registered[ 1] && sel[ 3] && sel[ 1] && sel[ 0];
assign masked[ 2] = registered[ 2] && sel[ 4] && sel[ 1] && sel[ 0];
assign masked[ 3] = registered[ 3] && sel[ 5] && sel[ 1] && sel[ 0];
assign masked[ 4] = registered[ 4] && sel[ 6] && sel[ 1] && sel[ 0];
assign masked[ 5] = registered[ 5] && sel[ 7] && sel[ 1] && sel[ 0];
assign masked[ 6] = registered[ 6] && sel[ 3] && sel[ 2] && sel[ 0];
assign masked[ 7] = registered[ 7] && sel[ 4] && sel[ 2] && sel[ 0];
assign masked[ 8] = registered[ 8] && sel[ 5] && sel[ 2] && sel[ 0];
assign masked[ 9] = registered[ 9] && sel[ 6] && sel[ 2] && sel[ 0];
assign masked[10] = registered[10] && sel[ 7] && sel[ 2] && sel[ 0];
assign masked[11] = registered[11] && sel[ 4] && sel[ 3] && sel[ 0];
assign masked[12] = registered[12] && sel[ 5] && sel[ 3] && sel[ 0];
assign masked[13] = registered[13] && sel[ 6] && sel[ 3] && sel[ 0];
assign masked[14] = registered[14] && sel[ 7] && sel[ 3] && sel[ 0];
assign masked[15] = registered[15] && sel[ 5] && sel[ 4] && sel[ 0];
assign masked[16] = registered[16] && sel[ 6] && sel[ 4] && sel[ 0];
assign masked[17] = registered[17] && sel[ 7] && sel[ 4] && sel[ 0];
assign masked[18] = registered[18] && sel[ 6] && sel[ 5] && sel[ 0];
assign masked[19] = registered[19] && sel[ 7] && sel[ 5] && sel[ 0];
assign masked[20] = registered[20] && sel[ 7] && sel[ 6] && sel[ 0];
assign masked[21] = registered[21] && sel[ 3] && sel[ 2] && sel[ 1];
assign masked[22] = registered[22] && sel[ 4] && sel[ 2] && sel[ 1];
assign masked[23] = registered[23] && sel[ 5] && sel[ 2] && sel[ 1];
assign masked[24] = registered[24] && sel[ 6] && sel[ 2] && sel[ 1];
assign masked[25] = registered[25] && sel[ 7] && sel[ 2] && sel[ 1];
assign masked[26] = registered[26] && sel[ 4] && sel[ 3] && sel[ 1];
assign masked[27] = registered[27] && sel[ 5] && sel[ 3] && sel[ 1];
assign masked[28] = registered[28] && sel[ 6] && sel[ 3] && sel[ 1];
assign masked[29] = registered[29] && sel[ 7] && sel[ 3] && sel[ 1];
assign masked[30] = registered[30] && sel[ 5] && sel[ 4] && sel[ 1];
assign masked[31] = registered[31] && sel[ 6] && sel[ 4] && sel[ 1];
assign masked[32] = registered[32] && sel[ 7] && sel[ 4] && sel[ 1];
assign masked[33] = registered[33] && sel[ 6] && sel[ 5] && sel[ 1];
assign masked[34] = registered[34] && sel[ 7] && sel[ 5] && sel[ 1];
assign masked[35] = registered[35] && sel[ 7] && sel[ 6] && sel[ 1];
assign masked[36] = registered[36] && sel[ 4] && sel[ 3] && sel[ 2];
assign masked[37] = registered[37] && sel[ 5] && sel[ 3] && sel[ 2];
assign masked[38] = registered[38] && sel[ 6] && sel[ 3] && sel[ 2];
assign masked[39] = registered[39] && sel[ 7] && sel[ 3] && sel[ 2];
assign masked[40] = registered[40] && sel[ 5] && sel[ 4] && sel[ 2];
assign masked[41] = registered[41] && sel[ 6] && sel[ 4] && sel[ 2];
assign masked[42] = registered[42] && sel[ 7] && sel[ 4] && sel[ 2];
assign masked[43] = registered[43] && sel[ 6] && sel[ 5] && sel[ 2];
assign masked[44] = !(|sel); // always TRUE condition (sel ==0)
always @(posedge clk) begin
if (ce) begin
registered[ 0] <= ST_NB_ND;
registered[ 1] <= PXCI0_NOT_CMDTOISSUE;
registered[ 2] <= PCTI_CTBAR_XCZ;
registered[ 3] <= PCTI_XCZ;
registered[ 4] <= NST_D2HR;
registered[ 5] <= NPD_NCA;
registered[ 6] <= CHW_DMAA;
registered[ 7] <= SCTL_DET_CHANGED_TO_4;
registered[ 8] <= SCTL_DET_CHANGED_TO_1;
registered[ 9] <= PXSSTS_DET_NE_3;
registered[10] <= PXSSTS_DET_EQ_1;
registered[11] <= NPCMD_FRE;
registered[12] <= FIS_OK;
registered[13] <= FIS_ERR;
registered[14] <= FIS_FERR;
registered[15] <= FIS_EXTRA;
registered[16] <= FIS_FIRST_INVALID;
registered[17] <= FR_D2HR;
registered[18] <= FIS_DATA;
registered[19] <= FIS_ANY;
registered[20] <= NB_ND_D2HR_PIO;
registered[21] <= D2HR;
registered[22] <= SDB;
registered[23] <= DMA_ACT;
registered[24] <= DMA_SETUP;
registered[25] <= BIST_ACT_FE;
registered[26] <= BIST_ACT;
registered[27] <= PIO_SETUP;
registered[28] <= NB_ND;
registered[29] <= TFD_STS_ERR;
registered[30] <= FIS_I;
registered[31] <= PIO_I;
registered[32] <= NPD;
registered[33] <= PIOX;
registered[34] <= XFER0;
registered[35] <= PIOX_XFER0;
registered[36] <= CTBAA_CTBAP;
registered[37] <= CTBAP;
registered[38] <= CTBA_B;
registered[39] <= CTBA_C;
registered[40] <= TX_ERR;
registered[41] <= SYNCESC_ERR;
registered[42] <= DMA_PRD_IRQ_PEND;
registered[43] <= X_RDY_COLLISION;
end
cond_r[ 0] <= |masked[ 7: 0];
cond_r[ 1] <= |masked[15: 8];
cond_r[ 2] <= |masked[23:16];
......
helpers/ahci_fsm_sequence.py
View file @ e94b62c6
......@@ -53,7 +53,7 @@ actions = ['NOP',
# FIS_TRANSMIT
'CLEAR_CMD_TO_ISSUE',
# DMA
'DMA_ABORT', 'DMA_PRD_IRQ_CLEAR',
'DMA_ABORT*', 'DMA_PRD_IRQ_CLEAR',
# SATA TRANSPORT/LINK/PHY
'XMIT_COMRESET', 'SEND_SYNC_ESC*', 'SET_OFFLINE', 'R_OK', 'R_ERR',
# FIS TRANSMIT/WAIT DONE
......@@ -158,7 +158,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'P:NotRunning'},
{LBL:'P:StartBitCleared', ACT: 'PXCI0_CLEAR'}, # pxci0_clear
{ ACT: 'DMA_ABORT'}, # dma_cmd_abort (should eventually clear PxCMD.CR)?
{ ACT: 'DMA_ABORT*'}, # dma_cmd_abort (should eventually clear PxCMD.CR)?
{ ACT: 'PCMD_CR_CLEAR'}, # pcmd_cr_reset
{ ACT: 'XFER_CNTR_CLEAR'}, # clear_xfer_cntr
......@@ -477,6 +477,7 @@ def condition_mux_verilog(conditions, condition_vals, module_name, fanout, file=
module %s (
input clk,
input ce, // enable recording all conditions
input [%2d:0] sel,
output condition,"""
v=max(condition_vals.values())
......@@ -485,15 +486,14 @@ module %s (
num_inputs += 1
v >>= 1
maximal_length = max([len(n) for n in conditions])
# numregs = (len(conditions) + fanout - 1) // fanout
numregs = (len(conditions) + fanout) // fanout # one more bit for 'always' (sel == 0)
header = header_template%(module_name, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
print(header,file=file)
for input_name in conditions[:len(conditions)-1]:
print(" input %s,"%(input_name),file=file)
print(" input %s);\n"%(conditions[-1]),file=file)
# print(" wire [%2d:0] masked;"%(len(conditions)-1),file=file)
print(" wire [%2d:0] masked;"%(len(conditions)),file=file)
print(" input %s,"%(input_name), file=file)
print(" input %s);\n"%(conditions[-1]), file=file)
print(" wire [%2d:0] masked;"%(len(conditions)), file=file)
print(" reg [%2d:0] registered;"%(len(conditions) -1),file=file)
if numregs > 1:
print(" reg [%2d:0] cond_r;\n"%(numregs-1),file=file)
else:
......@@ -505,7 +505,8 @@ module %s (
print(" assign condition = cond_r;\n",file=file)
for b in range (len(conditions)):
print(" assign masked[%2d] = %s %s"%(b, conditions[b] , " "*(maximal_length - len(conditions[b]))),end="",file=file)
# print(" assign masked[%2d] = %s %s"%(b, conditions[b] , " "*(maximal_length - len(conditions[b]))),end="",file=file)
print(" assign masked[%2d] = registered[%2d] "%(b, b),end="",file=file)
d = condition_vals[conditions[b]]
for nb in range(num_inputs-1,-1,-1):
......@@ -514,7 +515,13 @@ module %s (
print (";", file=file)
print(" assign masked[%2d] = !(|sel); // always TRUE condition (sel ==0)"%(len(conditions)), file=file)
print ("\n always @(posedge clk) begin", file=file)
print ("\n always @(posedge clk) begin", file=file)
print (" if (ce) begin", file=file)
for b in range (len(conditions)):
print(" registered[%2d] <= %s;"%(b, conditions[b]),file=file)
print (" end", file=file)
for nb in range (numregs):
ll = nb * fanout
# hl = min(ll + fanout, len(conditions)) -1
......
includes/ahxi_fsm_code.vh
View file @ e94b62c6
......@@ -15,6 +15,6 @@
, .INIT_0E (256'h00F60082011000ED24FB250200C000390401011000E624FB2502018000500101)
, .INIT_0F (256'h0100020101000021021001000021004400F6000000F6011000F424FB250200C0)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000390041000001000000)
, .INITP_00 (256'hC8220098170902401E272722222800309418800820809C802018880022222222)
, .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222)
, .INITP_01 (256'h22082227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000082)
py393sata/x393sata.py
View file @ e94b62c6
......@@ -57,10 +57,12 @@ FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c
MAXI1_ADDR = 0x80000000
DATASCOPE_ADDR = 0x1000 + MAXI1_ADDR
COMMAND_HEADER0_OFFS = 0x800 # offset of the command header 0 in MAXI1 space
COMMAND_HEADER0_OFFS = 0x800 # offset of the command header 0 in MAXI1 space
COMMAND_BUFFER_OFFSET = 0x0 # Just at the beginning of available memory
COMMAND_BUFFER_SIZE = 0x100 # 256 bytes - 128 before PRDT, 128+ - PRDTs (16 bytes each)
PRD_OFFSET = 0x80 # Start of the PRD table
FB_OFFS = 0xc00 # Needs 0x100 bytes
DATAIN_BUFFER_OFFSET = 0x10000
DATAIN_BUFFER_SIZE = 0x10000
IDENTIFY_BUF = 0 # Identify receive buffer offset in DATAIN_BUFFER, in bytes
......@@ -87,7 +89,13 @@ FIS_BIST = 0x58
FIS_PIOS = 0x5f
FIS_SDB = 0xa1
#ATA commands
ATA_IDFY = 0xEC
ATA_IDFY = 0xec # Identify command
ATA_WDMA = 0xca # Write to device in DMA mode
ATA_WBUF_PIO = 0xe8 # Write 512 bytes to device buffer in PIO mode
ATA_WBUF_DMA = 0xeb # Write 512 bytes to device buffer in DMA mode
ATA_RDMA = 0xc8 # Read from device in DMA mode
ATA_RBUF_PIO = 0xe4 # Read 512 bytes from device buffer in PIO mode
ATA_RBUF_DMA = 0xe9 # Read 512 bytes from device buffer in DMA mode
class x393sata(object):
DRY_MODE= True # True
......@@ -436,13 +444,15 @@ class x393sata(object):
"""
shutil.copy2(src, dst)
def setup_pio_read_identify_command(self, prd_irqs = None):
def setup_pio_read_identify_command(self, do_not_start = False, prd_irqs = None):
"""
@param do_not_start - do not actually launch the command by writing 1 to command_issue (CI) bit in PxCI register
@param prd_irqs - None or a tuple/list with per-PRD interrupts
"""
# clear system memory for command
# clear system memory for the command
for a in range(64):
self.x393_mem.write_mem(COMMAND_ADDRESS + 4*a, 0)
#Setup command table in system memory
self.x393_mem.write_mem(COMMAND_ADDRESS + 0,
FIS_H2DR | # FIS type - H2D register (0x27)
(0x80 << 8) | # set C = 1
......@@ -454,7 +464,7 @@ class x393sata(object):
prdt_int = 0
if prd_irqs:
prdt_int = (0,1)[prd_irqs[0]]
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (3 << 2), DATAIN_ADDRESS + (prdt_int << 31) | 511) # 512 bytes in this PRDT)
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (3 << 2), (prdt_int << 31) | 511) # 512 bytes in this PRDT)
# Setup command header
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (0 << 2),
(5 << 0) | # 'CFL' - number of DWORDs in this CFIS
......@@ -467,8 +477,9 @@ class x393sata(object):
(1 << 16)) # 'PRDTL' - number of PRDT entries (just one)
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2),
(COMMAND_ADDRESS) & 0xffffffc0) # 'CTBA' - Command table base address
# Make it flush?
# Write some junk to the higher addresses of the CFIS
#Only was needed for debugging, removing
"""
for i in range (10):
self.x393_mem.write_mem(COMMAND_ADDRESS + 4*(i+1),
(4 * i + 1) |
......@@ -476,20 +487,185 @@ class x393sata(object):
((4 * i + 3) << 16) |
((4 * i + 4) << 24))
"""
# Make it flush (dumb way - write each cache line (32 bytes) something?
for i in range (4096):
self.x393_mem.write_mem(COMMAND_ADDRESS + 32 * i, self.x393_mem.read_mem(COMMAND_ADDRESS + 32 * i))
# print("Running flush_mem()")
# self.flush_mem() # Did not worked, caused error
#mem.write_mem(0x80000118,0x11)
# Set PxCMD.ST bit (it may already be set)
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCMD'), 0x11) # .ST and .FRE bits (FRE is readonly 1 anyway)
# Set Command Issued
if do_not_start:
print ('Run the following command to start the comand:')
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
else:
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("Command table data:")
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x20,4)
print("Memory read data:")
print("_=mem.mem_dump (0x%x, 0x100, 2)"%(DATAIN_ADDRESS + IDENTIFY_BUF))
self.x393_mem.mem_dump (DATAIN_ADDRESS + IDENTIFY_BUF, 0x100,2)
for i in range (4066):
def dd_read_dma(self, skip, count = 1, do_not_start = False, prd_irqs = None): #TODO: Add multi-PRD testing
"""
Read device to memory, use single PRD table
@param skip - start block number
@param count - number of blocks to read
@param do_not_start - do not actually launch the command by writing 1 to command_issue (CI) bit in PxCI register
@param prd_irqs - None or a tuple/list with per-PRD interrupts
"""
if skip > (1 << 24):
raise ValueError ("This program supports only 24-bit LBA")
if count > 256:
raise ValueError ("This program supports only 8 bit count")
# clear system memory for the command
for a in range(64):
self.x393_mem.write_mem(COMMAND_ADDRESS + 4*a, 0)
#Setup command table in system memory
self.x393_mem.write_mem(COMMAND_ADDRESS + 0,
FIS_H2DR | # FIS type - H2D register (0x27)
(0x80 << 8) | # set C = 1
(ATA_RDMA << 16) | # Command = 0xEC (IDFY)
( 0 << 24)) # features = 0 ?
self.x393_mem.write_mem(COMMAND_ADDRESS + 4, skip) # LBA 24 bits
self.x393_mem.write_mem(COMMAND_ADDRESS + 12, count & 0xff) # count field (0 means 256 blocks)
# Other DWORDs are reserved/0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (0 << 2), DATAIN_ADDRESS)
prdt_int = 0
if prd_irqs:
prdt_int = (0,1)[prd_irqs[0]]
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (3 << 2), (prdt_int << 31) | ((count * 512) -1)) # count * 512 bytes in this PRDT)
# Setup command header
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (0 << 2),
(5 << 0) | # 'CFL' - number of DWORDs in this CFIS
(0 << 5) | # 'A' Not ATAPI
(0 << 6) | # 'W' Not write to device
(1 << 7) | # 'P' Prefetchable = 1
(0 << 8) | # 'R' Not a Reset
(0 << 9) | # 'B' Not a BIST
(1 << 10) | # 'C' Do clear BSY/CI after transmitting this command
(1 << 16)) # 'PRDTL' - number of PRDT entries (just one)
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2),
(COMMAND_ADDRESS) & 0xffffffc0) # 'CTBA' - Command table base address
# Make it flush (dumb way - write each cache line (32 bytes) something?
for i in range (4096):
self.x393_mem.write_mem(COMMAND_ADDRESS + 32 * i, self.x393_mem.read_mem(COMMAND_ADDRESS + 32 * i))
# print("Running flush_mem()")
# self.flush_mem() # Did not worked, caused error
#mem.write_mem(0x80000118,0x11)
# Set PxCMD.ST bit (it may already be set)
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCMD'), 0x11) # .ST and .FRE bits (FRE is readonly 1 anyway)
# Set Command Issued
if do_not_start:
print ('Run the following command to start the comand:')
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
else:
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("Command table data:")
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x20,4)
print("Memory read data:")
print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(DATAIN_ADDRESS, count * 0x200))
self.x393_mem.mem_dump (DATAIN_ADDRESS, count * 0x200, 1)
def dd_write_dma(self, skip, count = 1, use_read_buffer = False, do_not_start = False, prd_irqs = None): #TODO: Add multi-PRD testing
"""
Write device from memory, use single PRD table
@param skip - start block number
@param count - number of blocks to read
@param use_read_buffer - write from the same memory as was used to receive data from device (False - use different memory range)
@param do_not_start - do not actually launch the command by writing 1 to command_issue (CI) bit in PxCI register
@param prd_irqs - None or a tuple/list with per-PRD interrupts
"""
if skip > (1 << 24):
raise ValueError ("This program supports only 24-bit LBA")
if count > 256:
raise ValueError ("This program supports only 24-bit LBA")
data_buf = (DATAOUT_ADDRESS, DATAIN_ADDRESS) [use_read_buffer]
# clear system memory for the command
for a in range(64):
self.x393_mem.write_mem(COMMAND_ADDRESS + 4*a, 0)
#Setup command table in system memory
self.x393_mem.write_mem(COMMAND_ADDRESS + 0,
FIS_H2DR | # FIS type - H2D register (0x27)
(0x80 << 8) | # set C = 1
(ATA_WDMA << 16) | # Command = 0xEC (IDFY)
( 0 << 24)) # features = 0 ?
self.x393_mem.write_mem(COMMAND_ADDRESS + 4, skip) # LBA 24 bits
self.x393_mem.write_mem(COMMAND_ADDRESS + 12, count & 0xff) # count field (0 means 256 blocks)
# Other DWORDs are reserved/0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (0 << 2), data_buf)
prdt_int = 0
if prd_irqs:
prdt_int = (0,1)[prd_irqs[0]]
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (3 << 2), (prdt_int << 31) | ((count * 512) -1)) # count * 512 bytes in this PRDT)
# Setup command header
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (0 << 2),
(5 << 0) | # 'CFL' - number of DWORDs in this CFIS
(0 << 5) | # 'A' Not ATAPI
(1 << 6) | # 'W' Is write to device
(1 << 7) | # 'P' Prefetchable = 1
(0 << 8) | # 'R' Not a Reset
(0 << 9) | # 'B' Not a BIST
(1 << 10) | # 'C' Do clear BSY/CI after transmitting this command
(1 << 16)) # 'PRDTL' - number of PRDT entries (just one)
self.x393_mem.write_mem(MAXI1_ADDR + COMMAND_HEADER0_OFFS + (2 << 2),
(COMMAND_ADDRESS) & 0xffffffc0) # 'CTBA' - Command table base address
# Make it flush (dumb way - write each cache line (32 bytes) something?
for i in range (4096):
self.x393_mem.write_mem(COMMAND_ADDRESS + 32 * i, self.x393_mem.read_mem(COMMAND_ADDRESS + 32 * i))
# print("Running flush_mem()")
# self.flush_mem()
# self.flush_mem() # Did not worked, caused error
#mem.write_mem(0x80000118,0x11)
# Set PxCMD.ST bit (it may already be set)
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCMD'), 0x11) # .ST and .FRE bits (FRE is readonly 1 anyway)
# Set Command Issued
#self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("_=mem.mem_dump (0x%x, 0x20,4)"%(COMMAND_ADDRESS))
if do_not_start:
print ('Run the following command to start the comand:')
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
else:
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__PxCI'), 1)
print("Command table data:")
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
print("Datascope (debug) data:")
print("_=mem.mem_dump (0x%x, 0x20,4)"%(DATASCOPE_ADDR))
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x20,4)
print("mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)")
self.x393_mem.mem_dump (DATASCOPE_ADDR, 0x20,4)
#print("Memory read data:")
#print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(data_buf, count * 0x200))
#self.x393_mem.mem_dump (data_buf, count * 0x200, 1)
"""
ATA_IDFY = 0xec # Identify command
ATA_WDMA = 0xca # Write to device in DMA mode
ATA_WBUF_PIO = 0xe8 # Write 512 bytes to device buffer in PIO mode
ATA_WBUF_DMA = 0xeb # Write 512 bytes to device buffer in DMA mode
ATA_RDMA = 0xc8 # Read from device in DMA mode
ATA_RBUF_PIO = 0xe4 # Read 512 bytes from device buffer in PIO mode
ATA_RBUF_DMA = 0xe9 # Read 512 bytes from device buffer in DMA mode
_=mem.mem_dump(0xf800b000,10,4)
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x11) # ST & FRE
......@@ -504,13 +680,60 @@ mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata()
sata.bitstream()
sata.reg_status()
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x11)
sata.reset_ie(), sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.setup_pio_read_identify_command()
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie(), sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.dd_read_dma(0x867,1)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x100,4)
mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)
_=mem.mem_dump (0x80001000, 0x20,4)
_=mem.mem_dump (0x38110000, 0x100,4)
sata.reset_ie()
sata.dd_read_dma(0x867, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie()
sata.dd_read_dma(0x865, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie()
sata.dd_read_dma(0x860, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reset_ie()
sata.dd_read_dma(0x01, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x10)
sata.vsc3304.connection_status()
......@@ -534,8 +757,8 @@ _=mem.mem_dump (0x80001000, 0x20,4)
mem.maxi_base()
hex(mem.read_mem(0x80000180))
mem.mem_dump (0x80000000, 0x200,1)
_=mem.mem_dump (0x80000000, 0x100,4)
_=mem.mem_dump (0x80000000, 0x200,1)
_=mem.mem_dump (0x80000000, 0x400,4)
sata.reset_ie(),sata.reset_device(), sata.reg_status(), hex(mem.read_mem(0x80000ff0))
......@@ -546,6 +769,8 @@ _=mem.mem_dump (0x80001000, 0x10,4)
_=mem.mem_dump (0x80001000, 0x20,4)
_=mem.mem_dump (0x27900000, 0x20,4)
for i in range (1024):
mem.write_mem(0x27900000 + 32*i, mem.read_mem(0x27900000 + 32*i))
......@@ -568,6 +793,31 @@ _=mem.mem_dump (0x80001000, 0x20,4)
mem.write_mem(0x80000118,0x10)
idfy:
Command table data:
_=mem.mem_dump (0x38100000, 0x10,4)
0x38100000:00ec8027 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x38100040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Datascope (debug) data:
_=mem.mem_dump (0x80001000, 0x20,4)
0x80001000:5e2e8027 1c1f0000 18000000 10010000 80020000 00000005 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80001040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
DMA read:
0x38100000:00c88027 00000867 00000000 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x38100040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Datascope (debug) data:
_=mem.mem_dump (0x80001000, 0x20,4)
0x80001000:5e2f0000 1c100000 18010000 10020000 80030000 00000005 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x80001040:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>>> sata.setup_pio_read_identify_command()
>>> sata.reg_status()
......@@ -617,6 +867,62 @@ HBA_PORT__PxCI: 0x00000000 [80000138]
0x38110380:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x381103c0:00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x38110000:3fff0040 0010c837 00000000 0000003f 00000000 33393133 34303535 33353030 20202020 20202020 00000000 58320000 32303331 53613020 69736e44 53446b20
0x38110040:46313653 32384d31 20204720 20202020 20202020 20202020 20202020 80012020 2f004000 02004000 00070000 00103fff fc10003f 010100fb 0ee7c2b0 00070000
0x38110080:00780003 00780078 40200078 00000000 00000000 001f0000 0084870e 0040014c 002801f0 7d09346b 34694123 4123bc09 0001407f 00fe0006 0000fffe 00000000
0x381100c0:00000000 00000000 0ee7c2b0 00000000 00100000 00004000 b44a5001 2d633bf2 00000000 00000000 00000000 401c0000 0000401c 00000000 00000000 00000000
0x38110100:00000021 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
0x38110140:00000000 00000000 00000000 00000000 0001000b 00000000 00000000 00000000 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020
0x38110180:20202020 20202020 20202020 20202020 20202020 20202020 20202020 00000000 40000000 00000000 00000000 00000000 00010000 00000000 00000000 0000103f
0x381101c0:00000000 00000000 00000000 00000000 00000000 00800001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 afa50000
7.12.7.91 Word 255: Integrity word
If bits 7:0 of this word contain the Checksum Validity Indicator A5h, then bits 15:8 contain the data structure
checksum. The data structure checksum is the two's complement of the sum of all bytes in words 0..254 and the
byte consisting of bits 7:0 in word 255. Each byte shall be added with unsigned arithmetic, and overflow shall be
ignored. The sum of all 512 bytes is zero if the checksum is correct.
andrey@shuttle-andrey:~/git/x393_sata/debug$ sudo dd if=/dev/sdd skip=2151 count=2 | hexdump -C
00000000 92 bd c5 05 a3 7d 07 29 05 ad 05 40 ad 24 4a 3d |.....}.)...@.$J=|
00000010 3e c0 d5 d6 b1 6a b4 dc ae a0 00 b6 45 a5 44 28 |>....j......E.D(|
00000020 24 f5 95 9b a8 ff f4 4f 2f 1f c7 6a 0c f5 b0 9c |$......O/..j....|
00000030 9b fa e1 f4 b1 27 ee 5a 8f fa cc 71 30 d3 55 75 |.....'.Z...q0.Uu|
00000040 61 3a 19 b1 d7 6d 36 88 7f 64 d1 3c ac 03 b5 ed |a:...m6..d.<....|
00000050 97 42 d5 09 87 18 f5 12 4b 76 ab a0 d7 8d 20 b7 |.B......Kv.... .|
00000060 b7 d6 ca de b5 ec c7 7b e0 20 2e 07 36 a7 66 76 |.......{. ..6.fv|
00000070 c7 dd 88 c4 ee 20 1a 48 7d 4a d3 be 7e d0 74 88 |..... .H}J..~.t.|
00000080 e1 49 4c 52 35 ba 5b 77 35 66 0a 78 5a 13 35 72 |.ILR5.[w5f.xZ.5r|
00000090 58 85 18 c8 2e e7 bb f1 e8 4f 92 aa 03 a6 6b fc |X........O....k.|
000000a0 6f a3 21 70 aa 01 f4 8a 88 d1 a2 f7 4c 95 20 78 |o.!p........L. x|
000000b0 4f 5d d4 c0 f4 2b d9 15 ad 4b 6d e2 a5 8f b2 28 |O]...+...Km....(|
000000c0 ed 6b f7 ee 79 c9 e9 9a a1 7c 79 8c c9 01 5f 3f |.k..y....|y..._?|
000000d0 98 91 1f 47 3b 25 8d 3e 3c e0 c6 85 3f 23 06 ac |...G;%.><...?#..|
000000e0 ef 28 e0 21 a4 8a 15 85 75 f9 8f 57 23 52 3d 9d |.(.!....u..W#R=.|
000000f0 5e 32 58 e8 d7 45 11 4b fa a7 f2 a9 0b 82 48 52 |^2X..E.K......HR|
00000100 88 d3 33 25 2e 07 23 21 a5 c6 3e a4 38 ab b6 07 |..3%..#!..>.8...|
00000110 dc 31 5f f6 0c ec 2c 04 22 d7 fc fd 8a 93 0e 8a |.1_...,.".......|
00000120 4b b6 b7 c1 53 21 26 b8 3d 2a da 2f db 03 01 8f |K...S!&.=*./....|
00000130 76 09 89 42 4a a8 fc f8 28 ec 22 a9 2a 0b 7c 1d |v..BJ...(.".*.|.|
00000140 6b c9 50 02 e8 00 dd 56 0b 69 44 ed 68 8d e1 aa |k.P....V.iD.h...|
00000150 9a e2 f7 c0 54 bc f9 99 7c 14 90 85 8b fe 63 10 |....T...|.....c.|
00000160 95 be a1 d2 39 2c 90 a5 6e f7 27 84 45 25 8e 44 |....9,..n.'.E%.D|
00000170 a9 63 ee 76 bf dd 52 32 23 82 36 43 56 a4 86 f0 |.c.v..R2#.6CV...|
00000180 cd 8c f9 b6 88 a3 fd ba de de 4e cc d8 30 91 79 |..........N..0.y|
00000190 f6 a6 c2 7c dd 9d b4 24 ae 82 ad 36 27 b1 a8 cc |...|...$...6'...|
000001a0 f4 47 d8 db 84 7c e3 d4 2e 89 1c bf 47 ca 8c 4c |.G...|......G..L|
000001b0 d1 10 39 04 8b 26 94 ec b7 dd 87 36 53 6d f8 d5 |..9..&.....6Sm..|
000001c0 5d 43 4a da a2 b9 c2 fd d8 61 94 8b 4a 16 f3 03 |]CJ......a..J...|
000001d0 26 b6 43 36 ef ee aa dc f6 e4 d3 3e 9c 0a b3 a8 |&.C6.......>....|
000001e0 6a 91 ef 9b 10 b4 06 03 41 38 96 59 dc c2 bb 0a |j.......A8.Y....|
000001f0 6f 6c f0 3b ac 78 9d 01 fe 9a 95 20 bf d7 83 e0 |ol.;.x..... ....|
00000200 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
*
2+0 records in
2+0 records out
......
tb/tb_ahci.tf
View file @ e94b62c6
......@@ -762,15 +762,35 @@ localparam SYS_MEM_SIZE = 16384; // bytes - size of system memory
localparam COMMAND_TABLE = 32'h3f00; // 256 bytes for a command table in the system memory
localparam IDENTIFY_BUF = 32'h3d00; // 512 bytes for a command table in the system memory
localparam PRD_OFFSET = 'h80; // start of PRD table - 128-th byte in command table
localparam ATA_IDFY = 'hec; // Identify command
localparam ATA_WDMA = 'hca; // Identify command
localparam ATA_IDFY = 'hec; // Identify command
localparam ATA_WDMA = 'hca; // Write to device in DMA mode
localparam ATA_WBUF_PIO = 'he8; // Write 512 bytes to device buffer in PIO mode @SuppressThisWarning VEditor - not yet used
localparam ATA_WBUF_DMA = 'heb; // Write 512 bytes to device buffer in DMA mode @SuppressThisWarning VEditor - not yet used
localparam ATA_RDMA = 'hc8; // Read from device in DMA mode @SuppressThisWarning VEditor - not yet used
localparam ATA_RBUF_PIO = 'he4; // Read 512 bytes from device buffer in PIO mode @SuppressThisWarning VEditor - not yet used
localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mode @SuppressThisWarning VEditor - not yet used
reg [31:0] sysmem[0:4095];
// connect system memory ty AXI_NP RD and WR channels
// assign HCLK = dut.ps7_i.SAXIHP3ACLK; // shortcut name
// afi loopback
assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
// This is for no-delay memory
// assign #1 afi_sim_rd_valid = afi_sim_rd_ready;
// Make long delay for the first memory read, zero - for the next
reg afi_sim_rd_ready_r;
integer read_system_delay;
localparam SYSTEM_MEMORY_READ_LATENCY = 10; // HCLK cycles
always @ (posedge HCLK) begin
if (!afi_sim_rd_ready) read_system_delay <= SYSTEM_MEMORY_READ_LATENCY;
else if (read_system_delay != 0) read_system_delay <= read_system_delay - 1;
afi_sim_rd_ready_r <= afi_sim_rd_ready && (read_system_delay == 0);
end
assign #1 afi_sim_rd_valid = afi_sim_rd_ready && afi_sim_rd_ready_r;
assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;
assign #1 afi_sim_wr_ready = 1; // afi_sim_wr_valid;
assign #1 afi_sim_bresp_latency=4'h5;
......@@ -809,7 +829,9 @@ localparam ATA_WDMA = 'hca; // Identify command
task setup_pio_read_identify_command_simple;
input integer data_len;
input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
integer i;
begin
// clear system memory for command
......@@ -822,7 +844,7 @@ localparam ATA_WDMA = 'hca; // Identify command
// All other 4 DWORDs are 0 for this command
// Set PRDT (single item) TODO: later check multiple small ones
sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF;
sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) | 511; // 512 bytes in this PRDT
sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) | (data_len-1); // 512 bytes in this PRDT
// Setup command header
maxigp1_writep ((CLB_OFFS32 + 0) << 2, (5 << 0) | // 'CFL' - number of DWORDs in thes CFIS
(0 << 5) | // 'A' Not ATAPI
......@@ -939,7 +961,7 @@ localparam ATA_WDMA = 'hca; // Identify command
// fill ATA command
sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR | // FIS type - H2D register (0x27)
('h80 << 8) | // set C = 1
(ATA_WDMA << 16) | // Command = 0xEC (IDFY)
(ATA_WDMA << 16) | // Command = 0xCA
( 0 << 24); // features = 0 ?
sysmem[(COMMAND_TABLE >> 2) + 1] = lba & 'hffffff; // 24 LSBs of LBA (48-bit require different ATA command)
sysmem[(COMMAND_TABLE >> 2) + 3] = 1; // 1 logical sector (0 means 256)
......@@ -1053,11 +1075,12 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");
// setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0
// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0
// setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
setup_pio_read_identify_command_simple(2560,1); // intentionally too long
/// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0
setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
`ifdef TEST_ABORT_COMMAND
// Abort command by clearing ST
......@@ -1080,6 +1103,15 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ);
// Reset command with abort_dma
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0
repeat (50) @(posedge CLK);
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // ST: 0 -> 1
// Print datascope - contents of the last CFIS sent
maxigp1_print ('h1000,"DATASCOPE 0"); //
maxigp1_print ('h1004,"DATASCOPE 1"); //
......@@ -1093,6 +1125,28 @@ initial begin //Host
// sysmem_print ('h1e81,'h180); // for shifted
sysmem_print ('h1e80,'h180); // Compact dump of "system memory" in hex word format
// Second time read identify:
// Prepare for D2H register FIS with interrupt bit set (expected to be sent after all data will be written to the device)
maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear DHR (D2H register FIS with "I" bit) interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one)
wait (~IRQ);
setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear that interrupt
wait (IRQ);
TESTBENCH_TITLE = "Got second Identify";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
maxigp1_print (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR");
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ);
// end of the second identify insertion
// Prepare for D2H register FIS with interrupt bit set (expected to be sent after all data will be written to the device)
maxigp1_writep (HBA_PORT__PxIS__DHRS__ADDR << 2, HBA_PORT__PxIS__DHRS__MASK); // clear DHR (D2H register FIS with "I" bit) interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts
......
tb_ahci_01.sav
View file @ e94b62c6
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sat Feb 6 02:12:42 2016
[*] Mon Feb 8 16:49:44 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160205183420632.fst"
[dumpfile_mtime] "Sat Feb 6 01:35:47 2016"
[dumpfile_size] 10099447
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160207225755387.fst"
[dumpfile_mtime] "Mon Feb 8 05:59:18 2016"
[dumpfile_size] 10376737
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 22906600
[timestart] 0
[size] 1823 1180
[pos] 1917 0
*-15.467498 23097166 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-23.562601 38842258 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -23,12 +23,10 @@
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
......@@ -46,7 +44,6 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
......@@ -58,14 +55,11 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 290
[signals_width] 278
[signals_width] 355
[sst_expanded] 1
[sst_vpaned_height] 573
@820
tb_ahci.TESTBENCH_TITLE[639:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_cntr[8:0]
@820
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
tb_ahci.DEVICE_TITLE[639:0]
tb_ahci.dev.DEV_TITLE[639:0]
......@@ -121,41 +115,8 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
@1001200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
@c00200
-tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in
@1401200
-group_end
@28
......@@ -928,6 +889,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@c00200
-ahci_fsm
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.dma_abort_done
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pcmd_st_cleared
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.asynq_rq
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
......@@ -955,16 +917,46 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@1401200
-group_end
@22
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_preload
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_actions
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_last_act_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions_w
@800028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_transitions[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.conditions_ce
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.condition
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.masked[44:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.registered[43:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.sel[7:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.condition_mux_i.cond_r[5:0]
@1001200
-group_end
@28
......@@ -1163,12 +1155,17 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1401200
-ahci_fsm
@c00200
@800200
-ahci_fis_receive
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
@28
@c08029
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
@1409201
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr[9:0]
@28
......@@ -1254,7 +1251,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
@1001200
-group_end
@1401200
@1000200
-ahci_fis_receive
@c00200
-ahci_fis_transmit
......@@ -1588,6 +1585,87 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
@c00200
-ahci_dma
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awid[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awlen[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wlast
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rvalid
@200
-
@800200
-abort
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.abort
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.done
@8028
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_racount[2:0]
@8022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_rcount[7:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wacount[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wcount[7:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.adav
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_arlen[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_arready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_arvalid
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_awid[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_awlen[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_awready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_awvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_rready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_rready_in
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_rready_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_rvalid
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wid[5:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wlast
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wlast_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.afi_wvalid_in
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.ard
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.ard_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.arwr
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.aw_count[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.aw_lengths_raddr[4:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.aw_lengths_waddr[4:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.awr
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.busy_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.dirty
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.done_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.drd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.hclk
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.hrst
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.r_count[7:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.w_count[7:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_hp_abort_i.wwr
@1000200
-abort
@28
tb_ahci.afi_sim_rd_ready
tb_ahci.afi_sim_rd_valid
@22
tb_ahci.afi_sim_rd_address[31:0]
tb_ahci.afi_sim_rd_data[63:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rvalid
......@@ -1597,6 +1675,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_busy
@1001200
-group_end
......@@ -1609,8 +1688,38 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rlast
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.hrst
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.mrst
@200
-
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wvalid
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wlast
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.dbg_afi_awvalid_cntr[7:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_set
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount[21:1]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_plus_data_addr[21:1]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.debug_out[31:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.debug_out1[31:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_len[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_addr_data_w
@800200
-fifo_h2d
@22
......@@ -3298,41 +3407,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_cntr[15:0]
@1000200
-states
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
@c00200
-tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata
@1401200
-group_end
@200
......@@ -3488,17 +3564,35 @@ tb_ahci.dev.linkSendPrim.type[111:0]
-device
@800200
-datascope
@200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in0[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in1[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in2[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in3[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_r[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_rd_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.dma_ct_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.chead_bsy
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.any_cmd_start
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.acfis_xmit_pend_r
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_acmd_left_r[4:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_acmd_left_out_r[4:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.fis_data_valid
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_stb
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_w
@c00023
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
@1401203
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.fsnd_cfis_xmit
......@@ -3557,8 +3651,6 @@ tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_cntr[8:0]
@1000200
-datascope
[pattern_trace] 1
......
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