Commit e151f409 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

verified/fixed multi-prd, non-aligned (start and length) receive buffer

parent 45736d4f

ahci/ahci_dma.v

+14 −8
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ module ahci_dma ( 


    wire           done_dev_wr; // finished PRD mem -> device

    wire           done_dev_rd; // finished PRD device -> mem

    wire           prd_done_hclk = done_dev_wr || done_dev_rd;

    wire           done_flush;  // done flushing last partial dword

    wire           cmd_done_hclk;

    wire           ct_done_mclk;
@@ -209,7 +210,7 @@ module ahci_dma ( 
    reg            data_next_burst;

    

//    wire           raddr_prd_rq = (|prds_left) && (ct_done || prd_done);

    wire           raddr_prd_rq = (|prds_left) && (first_prd_fetch || prd_done);

    wire           raddr_prd_rq = (|prds_left) && (first_prd_fetch || prd_done_hclk);

    

    reg            raddr_prd_pend;
@@ -244,7 +245,7 @@ module ahci_dma ( 
    

      

//    assign prd_done = done_dev_wr || done_dev_rd;

    assign cmd_done_hclk = ((ct_busy_r==2'b10) && (prdtl_mclk == 0)) || done_flush || done_dev_rd;

    assign cmd_done_hclk = ((ct_busy_r==2'b10) && (prdtl_mclk == 0)) || ((done_flush || done_dev_rd) && last_prd);

    assign ct_done = (ct_busy_r == 2'b10);

    assign first_prd_fetch = ct_over_prd_enabled == 2'b01;

    assign axi_set_raddr_w = axi_set_raddr_ready && (raddr_ct_pend || raddr_prd_pend || raddr_data_pend);
@@ -291,7 +292,9 @@ module ahci_dma ( 
        if (ct_re[1]) ct_data <=      ct_data_reg;

        

        if (ctba_ld) ctba_r <=        ctba[31:7];

        

        if (cmd_start) prdtl_mclk <=  prdtl;

        

        if (cmd_start) dev_wr_mclk <= dev_wr;

        

        if      (mrst)      cmd_busy <= 0;
@@ -443,14 +446,17 @@ module ahci_dma ( 
        // calculate afi_wlast - it is (qw_datawr_burst == 0), just use register qw_datawr_last

        

        if      (prd_wr)     qw_datawr_last <= qwcount[21:3] == 0;

        else if (afi_wvalid) qw_datawr_last <= qw_datawr_burst == 1;        

///     else if (afi_wvalid) qw_datawr_last <= qw_datawr_burst == 1;        

        else if (afi_wvalid) qw_datawr_last <= (qw_datawr_burst == 1) || (qw_datawr_last && !(|qw_datawr_left[21:3])); // last case - n*16 + 1 (last burst single)       

        

        if      (prd_wr)                                                      qw_datawr_burst <= (|qwcount[21:7])? 4'hf: qwcount[6:3];

        else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf

///     else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf

///     else if (afi_wvalid &&                   (qw_datawr_left[21:7] == 0)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf

        else if (afi_wvalid && qw_datawr_last && (qw_datawr_left[21:7] == 1)) qw_datawr_burst <= qw_datawr_left[6:3]; // if not last roll over to 'hf

        else if (afi_wvalid)                                                  qw_datawr_burst <= qw_datawr_burst - 1;

        

        if      (prd_wr)                       qw_datawr_left[21:3] <= qwcount[21:3];

        else if (afi_wvalid && qw_datawr_last) qw_datawr_left[21:7] <= qw_datawr_left[21:7] - 1;

        else if (afi_wvalid && qw_datawr_last) qw_datawr_left[21:7] <= qw_datawr_left[21:7] - 1; // can go negative - OK?

        

        // Count AXI IDs

        if      (hrst)             ct_id <= 0;
@@ -581,7 +587,7 @@ module ahci_dma ( 
        .rst       (hrst),            // input

        .src_clk   (hclk),            // input

        .dst_clk   (mclk),            // input

        .in_pulse  (done_dev_wr || done_dev_rd),         // input

        .in_pulse  (prd_done_hclk),   // input

        .out_pulse (prd_done),        // output

        .busy()                       // output

    );

tb/tb_ahci.tf

+91 −5
Original line number Diff line number Diff line
@@ -692,7 +692,7 @@ localparam ATA_IDFY = 'hec; // Identify command 
    

    wire [31:0] sysmem_di_high = ({{8{~afi_sim_wr_stb[7]}},{8{~afi_sim_wr_stb[6]}},{8{~afi_sim_wr_stb[5]}},{8{~afi_sim_wr_stb[4]}}} &

                                (sysmem[sysmem_dworda_wr[31:2]+1] ^ afi_sim_wr_data[63:32])) ^ afi_sim_wr_data[63:32];

    always @ (posedge HCLK) begin

    always @ (posedge HCLK) if (afi_sim_wr_ready && afi_sim_wr_valid) begin

        if (|afi_sim_wr_stb[3:0]) sysmem[sysmem_dworda_wr[31:2]    ] <= sysmem_di_low;

        if (|afi_sim_wr_stb[7:4]) sysmem[sysmem_dworda_wr[31:2] + 1] <= sysmem_di_high;

    end
@@ -716,7 +716,7 @@ localparam ATA_IDFY = 'hec; // Identify command 
    endtask

    

    

    task setup_pio_read_identify_command;

    task setup_pio_read_identify_command_simple;

        input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st

        integer i;

        begin
@@ -729,7 +729,7 @@ localparam ATA_IDFY = 'hec; // Identify command 
                                              ( 0 << 24);        // features = 0 ?

            // All other 4 DWORDs are 0 for this command

            // Set PRDT (single item) TODO: later check multiple small ones

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF + 2; // shift by 2 bytes

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF;

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) | 511; // 512 bytes in this PRDT

            // Setup command header

            maxigp1_writep       ((CLB_OFFS32 + 0) << 2,     (5 <<  0) | // 'CFL' - number of DWORDs in thes CFIS
@@ -747,6 +747,89 @@ localparam ATA_IDFY = 'hec; // Identify command 
            // relax and enjoy

        end

    endtask



    task setup_pio_read_identify_command_shifted;

        input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st

        integer i;

        begin

            // clear system memory for command

            for (i = 0; i < 64; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;

            // fill ATA command 

            sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR |         // FIS type - H2D register (0x27)

                                               ('h80 << 8) |      // set C = 1

                                               (ATA_IDFY << 16) | // Command = 0xEC (IDFY)

                                              ( 0 << 24);        // features = 0 ?

            // All other 4 DWORDs are 0 for this command

            // Set PRDT (single item) TODO: later check multiple small ones

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF + 2; // shift by 2 bytes

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 32) | 511; // 512 bytes in this PRDT

            // Setup command header

            maxigp1_writep       ((CLB_OFFS32 + 0) << 2,     (5 <<  0) | // 'CFL' - number of DWORDs in thes CFIS

                                                         (0 <<  5) | // 'A' Not ATAPI

                                                         (0 <<  6) | // 'W' Not write to device

                                                         (1 <<  7) | // 'P' Prefetchable = 1

                                                         (0 <<  8) | // 'R' Not a Reset

                                                         (0 <<  9) | // 'B' Not a BIST

//                                                         (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command

                                                         (1 << 10) | // 'C' Do clear BSY/CI after transmitting this command

                                                         (1 << 16)); // 'PRDTL' - number of PRDT entries (just one)

            maxigp1_writep       ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address

            // Set Command Issued

            maxigp1_writep       (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)

            // relax and enjoy

        end

    endtask



    task setup_pio_read_identify_command_multi4;

        input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st

        input integer nw1; // first segment lengtth (in words)

        input integer nw2; // second segment lengtth (in words)

        input integer nw3; // third segment lengtth (in words)

        

        integer nw4;

        integer i;

        

        begin

            nw4 = 256 - nw1 - nw2 - nw3; // total 512 bytes, 256 words

            // clear system memory for command

            for (i = 0; i < 64; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;

            // fill ATA command 

            sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR |         // FIS type - H2D register (0x27)

                                               ('h80 << 8) |      // set C = 1

                                               (ATA_IDFY << 16) | // Command = 0xEC (IDFY)

                                              ( 0 << 24);        // features = 0 ?

            // All other 4 DWORDs are 0 for this command

            // Set PRDT (four items)

            // PRDT #1

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  0] = SYS_MEM_START + IDENTIFY_BUF; // not shifted

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  3] = (prd_int[0] << 31) | (2 * nw1 - 1); // 2 * nw1 bytes

            // PRDT #2

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  4] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1);

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  7] = (prd_int[0] << 31) | (2 * nw2 - 1); // 2 * nw2 bytes

            // PRDT #3

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) +  8] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1) + (2 * nw2);

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 11] = (prd_int[0] << 31) | (2 * nw3 - 1); // 2 * nw3 bytes

            // PRDT #4

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 12] = SYS_MEM_START + IDENTIFY_BUF + (2 * nw1) + (2 * nw2) + (2 * nw3);

            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 15] = (prd_int[0] << 31) | (2 * nw4 - 1); // 2 * nw4 bytes

            

            // Setup command header

            maxigp1_writep       ((CLB_OFFS32 + 0) << 2,     (5 <<  0) | // 'CFL' - number of DWORDs in thes CFIS

                                                         (0 <<  5) | // 'A' Not ATAPI

                                                         (0 <<  6) | // 'W' Not write to device

                                                         (1 <<  7) | // 'P' Prefetchable = 1

                                                         (0 <<  8) | // 'R' Not a Reset

                                                         (0 <<  9) | // 'B' Not a BIST

//                                                         (0 << 10) | // 'C' Do not clear BSY/CI after transmitting this command

                                                         (1 << 10) | // 'C' Do clear BSY/CI after transmitting this command

                                                         (4 << 16)); // 'PRDTL' - number of PRDT entries (4)

            maxigp1_writep       ((CLB_OFFS32 +2 ) << 2, (SYS_MEM_START + COMMAND_TABLE) & 32'hffffffc0); // 'CTBA' - Command table base address

            // Set Command Issued

            maxigp1_writep       (HBA_PORT__PxCI__CI__ADDR << 2, 1); // 'PxCI' - Set 'Command issue' for slot 0 (the only one)

            // relax and enjoy

        end

    endtask



initial begin //Host

    wait (!RST);

//reg [639:0] TESTBENCH_TITLE = "RESET"; // to show human-readable state in the GTKWave
@@ -812,7 +895,9 @@ initial begin //Host 
    

    maxigp1_print        (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");

    

    setup_pio_read_identify_command(1); // prdt interrupt for entry 0

    setup_pio_read_identify_command_simple(1); // prdt interrupt for entry 0

//    setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0

//    setup_pio_read_identify_command_multi4(1,27,71,83); // prdt interrupt for entry 0

    maxigp1_print        (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");

    

    maxigp1_writep       (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
@@ -823,7 +908,8 @@ initial begin //Host 


    maxigp1_print        (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR");

    

    sysmem_print ('h1e81,'h180);

//    sysmem_print ('h1e81,'h180); // for shifted

    sysmem_print ('h1e80,'h180);

    

    $finish;

//HBA_PORT__PxIE__DHRE__MASK = 'h1;

tb_ahci_01.sav

+165 −83
Original line number Diff line number Diff line 
[*]

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] Wed Jan 27 06:51:42 2016

[*] Wed Jan 27 20:13:54 2016

[*]

[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126234218474.fst"

[dumpfile_mtime] "Wed Jan 27 06:43:12 2016"

[dumpfile_size] 6563895

[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160127131132886.fst"

[dumpfile_mtime] "Wed Jan 27 20:12:01 2016"

[dumpfile_size] 3824547

[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"

[timestart] 0

[size] 1823 1173

[timestart] 24704000

[size] 1823 1180

[pos] 1994 0

*-22.938511 25590250 19123334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-16.995279 25103334 23903334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] tb_ahci.

[treeopen] tb_ahci.dev.phy.

[treeopen] tb_ahci.dut.
@@ -34,8 +34,8 @@ 
[treeopen] tb_ahci.simul_axi_hp_wr_i.

[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.

[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.

[sst_width] 275

[signals_width] 256

[sst_width] 307

[signals_width] 331

[sst_expanded] 1

[sst_vpaned_height] 618

@820
@@ -435,7 +435,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0] 
-ahci_fis_receive

@1401200

-ahci_top

@800200

@c00200

-ahci_ctrl_stat

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
@@ -653,9 +653,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0] 
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]

(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]

(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]

@29

(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]

@28

(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]

@1001200

-group_end
@@ -740,7 +738,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2 
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3

@1401200

-ssts

@1000200

-ahci_ctrl_stat

@c00200

-axi_ahci_regs
@@ -755,7 +752,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access 
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst

@1401200

-axi_ahci_regs

@800200

@c00200

-ahci_fsm

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@@ -976,7 +973,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] 
@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn

tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st

@1000200

@1401200

-ahci_fsm

@c00200

-ahci_fis_receive
@@ -1270,7 +1267,7 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0] 
-fifo_wdata

@1401200

-simul_axi_hp_wr

@c00200

@800200

-ahci_dma

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.hrst
@@ -1382,23 +1379,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_next_burst 
@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_alen[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_len[3:0]

@800200

-sim_d2h

@200

-

@22

tb_ahci.sysmem_dworda_wr[31:2]

tb_ahci.sysmem_di_low[31:0]

tb_ahci.sysmem_di_high[31:0]

tb_ahci.afi_sim_wr_address[31:0]

tb_ahci.afi_sim_wr_stb[7:0]

tb_ahci.afi_sim_wr_data[63:0]

@28

tb_ahci.afi_sim_wr_ready

tb_ahci.afi_sim_wr_valid

@1000200

-sim_d2h

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_in[31:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_nfull
@@ -1440,6 +1420,124 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr 
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount_many

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount[7:0]

@200

-----

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arvalid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arready

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_alen[3:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arsize[1:0]

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready

tb_ahci.afi_sim_rd_valid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rvalid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rlast

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_rq

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_pend

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_addr[31:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0]

@800028

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_afi_re

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_ct_addr

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ctba_r[31:7]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_maddr[31:4]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_addr[4:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_re[1:0]

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_data[31:0]

@1001200

-group_end

@200

-

@22

tb_ahci.sysmem_dworda_rd[31:2]

tb_ahci.afi_sim_rd_data[63:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_maddr[31:4]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_done

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount[21:1]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_set

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_done_hclk

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_wr

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_rq

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.first_prd_fetch

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awaddr[31:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awvalid

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wdata[63:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wvalid

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awlen[3:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wlast

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_done_hclk

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_done

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prdtl[15:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prdtl_mclk[15:0]

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prds_left[15:0]

@1401200

-group_end

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.last_prd

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.done_flush

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.done_dev_rd

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.done_dev_wr

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_last

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_left[21:3]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wvalid

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_burst[3:0]

@c00200

-dma_d2h_fifo

@28
@@ -1462,7 +1560,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty_mclk 
@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din[31:0]

@28

[color] 1

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din_rdy

[color] 3

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.din_avail

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.waddr[4:0]
@@ -1476,7 +1576,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.flush_hclk 
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.flush_mclk

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.hrst

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.hclk

@800022

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]
@@ -1487,14 +1587,14 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0] 
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]

(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]

(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_nempty[7:0]

@1001200

@1401200

-group_end

@28

[color] 3

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.mclk

[color] 2

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_wr

@800022

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]
@@ -1505,9 +1605,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0] 
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]

(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]

(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full[7:0]

@1001200

@1401200

-group_end

@800022

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]
@@ -1518,7 +1618,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0] 
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]

(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]

(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_full2[7:0]

@1001200

@1401200

-group_end

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.waddr[4:0]
@@ -1547,55 +1647,37 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd_r 
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.raddr[3:0]

@1401200

-dma_d2h_fifo

@800200

-sim_d2h

@200

-----

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_araddr[31:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arvalid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arready

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_alen[3:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_arsize[1:0]

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready

tb_ahci.afi_sim_rd_valid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rvalid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rlast

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_rq

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_ct_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_pend

-

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_addr[31:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rdata[63:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0]

@800028

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

tb_ahci.sysmem_dworda_wr[31:2]

tb_ahci.sysmem_di_low[31:0]

tb_ahci.sysmem_di_high[31:0]

tb_ahci.afi_sim_wr_address[31:0]

tb_ahci.afi_sim_wr_stb[7:0]

tb_ahci.afi_sim_wr_data[63:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_afi_re

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_ct_addr

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ctba_r[31:7]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_maddr[31:4]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_addr[4:0]

tb_ahci.afi_sim_wr_ready

tb_ahci.afi_sim_wr_valid

@1000200

-sim_d2h

@c00200

-ahci_fis_receive

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_re[1:0]

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ct_data[31:0]

@1001200

-group_end

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in_ready

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in_valid

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_ready

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_valid

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_many

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_skipping_extra

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_extra_r

tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_prds_done

@200

-

@22

tb_ahci.sysmem_dworda_rd[31:2]

tb_ahci.afi_sim_rd_data[63:0]

@1401200

-ahci_fis_receive

@c00200

-top

@28
@@ -1759,7 +1841,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full 
-top

@200

-

@1401200

@1000200

-ahci_dma

@c00200

-link